Jobs at d-Matrix | HiringCafe

d-Matrix

Operations Program Manager, Senior Staff

Operations Program Manager

5+ years in manufacturing/operations program mgmt for high-volume hardware; NPI to mass production; strong PM and cross-functional skills.

ASIC Functional Test Engineering Intern

Pursuing MS in Electrical/Computer Engineering; strong Python; hardware-software integration; familiarity with I2C/SPI/JTAG/UART/GPIO; ASIC concepts; lab-ready; onsite in Santa Clara, CA for 12 weeks.

Senior Supply Chain Manager 

Supply Chain Manager

10+ years in supply chain planning; strong NetSuite ERP; silicon/semiconductor supply chain; CM/EMS experience; analytical; startup mindset.

Supply Chain Analyst Intern

Pursuing bachelor's or master's in supply chain, IE, OR, analytics; strong Excel; AI tool experience; available Summer 2025; Santa Clara on-site; strong communication and analytical skills.

Hardware Qualification Engineer, Senior Staff 

Hardware Qualification Engineer

12+ years in hardware qualification or reliability for HPC/servers; BS/MS in engineering; expertise in JEDEC/IPC/Telcordia; proficient with high-speed test equipment; strong statistical skills.

Signal Integrity Engineer, Sr Staff

Signal Integrity Engineer

Senior Staff SI/PI Engineer with 12+ years in SI/PI design for high-performance platforms; 112G SerDes, PAM4, and measurement experience.

Manufacturing Engineering Intern – PCB

Manufacturing Engineering Intern

Pursuing or recently completed a B.S. or M.S. in Electrical Engineering; knowledge of PCB stack-up, IPC standards; experience with ECAD tools; SQL or data visualization; strong problem-solving.

System Power Engineer, Principal

System Power Engineer

12+ years in power electronics for HPC/GPU/data center hardware; BS/MS/PhD in EE; PDN modeling; high-current transients; MCM/Chiplet power.

PCB Design Engineer, Sr Staff

PCB Design Engineer

12+ years in high-speed PCB layout; Cadence Allegro Constraint Manager expert; scripting in SKILL/Python/TCL; proficient in 112G SerDes and high-density routing.

Power Performance Architect, Senior Staff - Accelerator Design 

Power Performance Architect

Master’s degree in electrical, computer engineering or computer science; 10-15 years in ASIC/SoC power estimation; experience with RTL, physical design, and architectural power estimation; design flow knowledge.

Systems Hardware Engineer, Principal 

10+ years in high-complexity hardware design; BS/MS in Electrical Engineering; Cadence Allegro/Orcad experience; SI/PI knowledge; high-speed design (32Gbps+); DFx/DFM/DFT; strong communication.

Principal Software ML Test Engineer

Lead test planning, automation, and execution for ML compute software; strong Python; 10+ years; MS/PhD preferred; experience with DL frameworks.

Analog Design Engieer (L4/L5)

Analog Design Engineer

BS/MS/PhD in Electrical Eng; 10+ years high-speed circuit design; Cadence/Synopsys; layout; Monte Carlo; cross-functional teamwork.

Principal Architect, Performance Analysis and Modeling

Expert in computer architecture, performance modeling, ML workloads; proficient in C/C++/Python; 8+ years (MS preferred) or 10+ years (BS) in related fields.

Manager, Software Engineering-Kernels

Software Engineering Kernels Manager

10+ years in computer engineering/math/physics with strong CS/architecture knowledge; proficient in C/C++, Python on Linux; experience with ML operators, HW accelerators, and embedded SIMD; leadership and ownership skills.

Digital Design Engineer, Micro-Architect, Principal

Digital Design Engineer

Master’s degree in EE/CE/CS; 12+ years in micro-architecture/RTL; Verilog/SystemVerilog; CAD/tool experience; strong collaboration.