Jobs at EnCharge AI | HiringCafe

EnCharge AI

Senior NPU Architect

BS or MS in EE, CS or related field; 5-8 years of relevant experience; PhD with 2-4 years preferred; strong knowledge of computer architecture, AI/ML workloads; C/C++, Python; Verilog/SystemVerilog.

HR Generalist

2-5 years of HR coordination/operations experience; HRIS (Workday/BambooHR/Rippling/UKG) and Greenhouse ATS experience; strong organizational, communication, and discretion.

Senior Emulation Engineer

BS/MS/Ph.D. in EE or CS with 7+ years of SoC design experience; experience with emulation platforms (Veloce/Palladium/ZeBu) and FPGA prototyping; PCIe/UCIe, LPDDR/HBM; RTL (Verilog/SystemVerilog); hardware debugging; scripting (Python/Tcl/Perl); UVM; SystemVerilog; C/C++ is a plus.

Physical Design Engineer

2–4 years in physical design in semiconductor; B.Tech/M.Tech in Electrical/Electronics Engineering; top-tier university; expert in Innovus; MCMM closure; low-power design (UPF/CPF); Python/Tcl; AI/ML-based EDA automation; Bangalore location.

Silicon Operations Manager

10+ years in semiconductor/manufacturing; expertise in LN-related production, test, and lifecycle management; strong communication and project leadership.

Staff / Senior Staff Engineer: Static Timing Analysis (STA) Lead

Static Timing Analysis Lead

9-14 years in STA/timing closure on advanced nodes; leadership and cross-functional collaboration; expertise in industry sign-off tools (PrimeTime/Tempus); MMMC & SDC/CDC; automation scripting.

Principal DFT Engineer

10+ years in DFT with at least 2 years in a leadership role; MBIST/SCANT/boundary scan expertise; experience with multi-node FinFET and low-power designs; familiarity with industry tools; salary $180k-$220k.

Hardware Technical Writer

5+ years in technical writing; experience with design specs, user manuals, and datasheets; collaborate with engineering; knowledge of ASIC/VLSI; degree in Electrical Engineering; proficient with Markdown, LaTeX, and MS Word.

Staff/Senior Staff Physical Design Floorplan & PDN Lead

Physical Design Floorplan & PDN Lead

10+ years in Physical Design with floorplanning and PDN expertise; tape-out experience at advanced nodes; strong scripting (Tcl/Python/Perl).

Staff DFT Engineer

9–10 years DFT experience, full tape-out cycle, expert in industry-standard DFT tools, STA, power-aware testing, startup-minded, and interest in Edge AI.

Software Engineer, Video Generation

Software Engineer

5+ years software engineering with backend or ML infrastructure focus; strong Python and systems language skills; experience building production APIs and serving systems.

Senior Physical Design Engineer

4–7 years in Physical Design; tape-out experience; Cadence Innovus/Tempus; Tcl and Python; strong PPA/STA/DRC-LVS skills; Bangalore hybrid work.

Principal Physical Design Engineer (RTL-to-GDSII)

Principal Physical Design Engineer

14+ years in Physical Design; sub-5nm tape-outs; Cadence Innovus suite; deep STA/PV/PI knowledge; TCL/Python scripting; strong cross-functional collaboration.

Lead DFT Engineer (Edge Computing)

Lead DFT Engineer

12+ years in DFT with at least 2 years in a leadership role; MBIST, SCAN, IJTAG, boundary scan; IST and POST; ATE bring-up; experience with FinFET nodes (7nm/5nm); multi-voltage/power-gated designs; proficiency with industry tools.

Principal Engineer, Static Timing Analysis (STA)

Principal Engineer

14+ years in VLSI with leadership experience; strong STA expertise; Cadence Tempus proficiency; leadership and cross-functional collaboration.

Senior Physical Design Engineer 

10+ years in physical design; Cadence tools; timing closure; low-power design; EM/IR checks; TCL/Python scripting; PD flow and floorplanning.

LLM Inference Deployment Engineer

Inference Deployment Engineer

Experience in LLM inference deployment, model optimization, and runtime engineering; strong Python and framework knowledge.

Embedded SW Engineer

Bachelor's in EE/CS; advanced C/C++ for OS/kernel; knowledge of RISC-V; PCIe IOMMU; virtualization; OS concepts; low-level debugging; performance tuning; strong communication.

Device Driver Engineer

3+ years device driver development; Linux/Windows drivers; PCIe, DMA, MMIO; C/C++ kernel programming; experience with AI accelerators; debugging and profiling tools.

AI Runtime Engineer

Bachelor’s or Master’s in CS/EE; 3+ years low-level runtime software for AI accelerators, GPUs, or HPC; strong C/C++; knowledge of task scheduling and memory hierarchy; hardware-aware optimizations; familiar with ONNX Runtime, TensorRT, TVM, OpenVINO.

AI Research Engineer

Master’s or Ph.D. in CS or Electrical Engineering; strong deep learning, model optimization, and quantization; Python/C++/CUDA/OpenCL; experience with PyTorch, TensorFlow, ONNX Runtime, TVM, TensorRT, OpenVINO.

AI Compiler Engineer

3+ years in compiler development focusing on AI/ML graph compilers; MLIR or Torch-FX; strong hardware optimization knowledge; CS/EE degree; C++/Python.