Eliyan

Digital - Principal Digital Verification Engineer

Principal Digital Verification Engineer

BS in Electrical Engineering; 15+ years of experience; strong UVM/SystemVerilog expertise; regression management; connectivity IPs; start-up experience.

DV - Staff Verification Engineer -  Serdes

Staff Verification Engineer

BS + 7 years of verification experience; 4+ years in PHY or high-speed interfaces; strong UVM/SystemVerilog expertise; experience with SerDes/PCIe PHY and VIP integration; leadership in mentoring and driving verification.

Digital - SerDes Digital Design Lead

SerDes Digital Design Lead

Lead digital design of high-speed SerDes IPs; 224G/448G data rates; RTL SystemVerilog; 12+ years; tapeout experience; advanced process nodes; strong technical leadership.

PD - Principal STA Signoff (Top-Level)

Principal STA Signoff

8–12 years in STA and timing closure for ASIC/SoC; strong timing constraints, ECO strategy, and cross-functional collaboration; Tcl and scripting experience; ability to drive signoff.

PD - Principal, Physical Design

Principal, Physical Design

8-12 years ASIC physical design experience; floorplanning, clocking, power planning, signoff through tapeout; EM/IR, PV, STA expertise.

PD - IP Lead – Sr Staff, Physical Design

Physical Design Lead

Senior-level physical design engineer with RTL-to-GDSII experience, PNR, STA, EM/IR, PV signoff, and flow optimization.

Staff AMS CAD Engineer

Masters in electrical engineering or related field; 3+ years AMS CAD/design support; proficient with EDA tools and scripting.

Digital - Staff Digital Design Engineer - PHY

Digital Design Engineer

8+ years digital frontend design with 4+ years in PHY or high-speed interfaces; 3+ tapeouts as design lead; strong SystemVerilog RTL; D2D PHY/SerDes expertise; CDC/UPF/SDC; leadership.

Digital - Principal Systems/DSP Engineer

Principal Systems/DSP Engineer

Lead DSP architecture for high-speed SerDes; model development; equalization and CDR; collaborate across teams; target 224G/448G on 3nm/2nm nodes.

Digital Design Engineer (title will reflect experience)

5+ years in high-speed digital design; strong SystemVerilog RTL/Assertions; Ethernet PMA/PCS; experience with IP integration and clocking; RTL synthesis and PPA optimization; familiarity with Ethernet 100G/200G/400G/800G standards.

Senior/Staff Packaging Engineer - Electro-Thermal

Packaging Engineer

Senior/Staff packaging engineer with electro-thermal simulation; onsite in Bay Area; full-time; PhD or Master’s with 5+ years; expert in electro-thermal and EDA tools.

I/O Architect

IO Architect

Expertise in architecture definition, chip micro-architecture, logic and physical design; strong scripting; 15+ years ideal; leadership experience; BS/MS in EE or related field.

Staff DFT Engineer

Proficient in modern DFT/DFx techniques; IEEE 1149.x/1687/1500/1838; Verilog RTL; TCL/shell scripting; 6-9 years experience; BS EE.

Staff Digital Verification Engineer

Digital Verification Engineer

6+ years in digital verification; MS/PhD in Electrical Engineering; strong SystemVerilog/UVM; Ethernet 100G+/200G+/400G experience; CI/CD and testbench development.

Principal / Sr. Principal Program Manager (Semiconductor)

Principal Program Manager

15+ years semiconductor program management; degree in Electrical/Computer Engineering; lead ASIC/platform programs; cross-functional/vendor management; strong communication.

Signal and Power Integrity Engineer

Expert in signal and power integrity with 5+ years experience; BS in EE required, MS preferred; onsite in Bay Area; no relocation.

Title	Location	Date
Digital - Principal Digital Verification Engineer Full Time · 15+ YOE Vancouver or California · Onsite	Vancouver or California Onsite	Apr 27, 2026
DV - Staff Verification Engineer - Serdes Full Time · 7+ YOE San Francisco or Vancouver or Toronto · Onsite	San Francisco or Vancouver or Toronto Onsite	Apr 8, 2026
Digital - SerDes Digital Design Lead Full Time · 12+ YOE Bay Area, California, United States · Onsite	Bay Area, California, United States Onsite	Feb 20, 2026
PD - Principal STA Signoff (Top-Level) Full Time · 8+ YOE United States · Onsite	United States Onsite	Feb 9, 2026
PD - Principal, Physical Design Full Time · 8+ YOE United States · Onsite	United States Onsite	Feb 9, 2026
PD - IP Lead – Sr Staff, Physical Design Full Time San Francisco, California, United States · Onsite	San Francisco, California, United States Onsite	Feb 9, 2026
Staff AMS CAD Engineer Full Time · 3+ YOE Bay Area, California, United States · Onsite	Bay Area, California, United States Onsite	Feb 6, 2026
Digital - Staff Digital Design Engineer - PHY Full Time · 8+ YOE San Francisco or Vancouver or Toronto · Onsite	San Francisco or Vancouver or Toronto Onsite	Dec 23, 2025
Digital - Principal Systems/DSP Engineer Full Time · 10+ YOE Bay Area, California, United States · Onsite	Bay Area, California, United States Onsite	Dec 22, 2025
Digital Design Engineer (title will reflect experience) Full Time · 5+ YOE United States · Onsite	United States Onsite	Dec 18, 2025
Senior/Staff Packaging Engineer - Electro-Thermal Full Time San Francisco, California, United States · Onsite	San Francisco, California, United States Onsite	Oct 20, 2025
I/O Architect Full Time · 15+ YOE San Francisco Bay Area, California, United States · Onsite	San Francisco Bay Area, California, United States Onsite	Sep 29, 2025
Staff DFT Engineer Full Time · 6+ YOE United States · Onsite	United States Onsite	Mar 10, 2025
Staff Digital Verification Engineer Full Time · 6+ YOE Vancouver, British Columbia, Canada · Onsite	Vancouver, British Columbia, Canada Onsite	Mar 5, 2025
Principal / Sr. Principal Program Manager (Semiconductor) Full Time · 15+ YOE United States · Onsite	United States Onsite	Feb 11, 2025
Signal and Power Integrity Engineer Full Time · 5+ YOE United States · Onsite	United States Onsite	May 5, 2023

Activities	Semiconductor designIntellectual property licensingIntegrated circuit developmentData interface engineeringSignal processing technology
Headquarters	US
Industries	SemiconductorsArtificial Intelligence
Name	Eliyan
Employees	78
Type	Private
Tagline	High-performance chiplet interconnect technology for artificial intelligence applications
Founded	2,021
Website	eliyan.com
Latest Funding Round	Series C
Latest Funding Year	2,026
Latest Funding Amount	50,000,000
Latest Investors	AMD VenturesArmMetaCoherent

Eliyan

About Eliyan