Mythic

Senior Test Engineer

Test Engineer

Senior hands-on semiconductor test engineer with experience in Wafer Sort, Final Package Test, ATE platforms, test programs, data analytics.

Senior Product Engineer

Product Engineer

Senior-level product engineering for semiconductor silicon; hands-on ownership of bring-up, characterization, yield, and production ramp; cross-functional collaboration; strong data fluency and problem solving.

Sr DFT Engineer

BS/MS/PhD in EE/ECE; 3+ years of industry experience; strong knowledge of DFT methodologies and SoC-level DFT integration; experience with JTAG, iJTAG, Scan, ATPG; proficiency with Synopsys/Tessent; Verilog/SystemVerilog; scripting (Perl, Tcl, Python)

Sr Staff /Staff DFT Engineer

DFT Engineer

Lead end-to-end DFT implementation and verification for complex SoC; MBIST, IJTAG, Scan, ATPG; pre-silicon test planning; collaborate with RTL, physical, STA, and analog design teams.

Mythic-ai.com

Senior Engineer: Physical Design

Physical Design Engineer

3+ years in Physical Design; degree in Electrical or Electronics Engineering; hands-on PD; expertise in PD flow; tapeouts; low-power design; automation using TCL/Perl/Python.

Senior Silicon Emulation Engineer

Silicon Emulation Engineer

Bachelor’s, Master’s, or Doctorate in EE/CE/CS; RTL emulation/verification experience; Linux, scripting; strong debugging skills.

Director/Principal Engineer: Physical Design

15+ years in physical design of complex SoCs; advanced-node tape-outs; floorplanning, placement, CTS, routing; power integrity, noise, thermal; analog/mixed-signal IP integration; cross-functional leadership.

Senior SoC RTL Design Engineer

Expert RTL design for SoCs; strong computer architecture; 5+ years in industry; experience with RTL, microarchitecture, DFT/DFD; timing, clocking; BS/MS/PhD in EE/CS/CSE; Python or Ruby beneficial.

Senior RTL Design Engineer

Experienced RTL design engineer with 8+ years in RTL, microarchitecture, and architecture development; strong Verilog/SystemVerilog and timing/EDA tools.

Senior Design Verification Engineer

8+ years in design verification; BS/MS/PhD in EE/CE/CS; experience with verification testbenches and UVM; strong architecture knowledge.

Compiler Engineer - Algorithmic Workloads Compilation

Compiler Engineer

Design compiler IRs and lowering strategies for algorithmic workloads with irregular or dynamic control flow; collaborate with hardware engineers; strong C++ and Python; familiarity with MLIR/LLVM.

Compiler Engineer – MLIR / PyTorch Infrastructure

3+ years in compiler or high-performance systems; proficiency in C++ and Python; MLIR experience; knowledge of IRs and lowering; interest in MLIR and PyTorch integration.

Compiler Engineer - Machine Learning Compiler

3+ years in compiler/high-performance systems; strong C++ (14/17/20) and Python; experience with IRs (SSA/graph-based), optimizations, and accelerators; collaboration across hardware and ML teams.

AI Algorithms/Software Engineer

5+ years of software experience in production; algorithm-heavy problem solving; bachelor's in Computer Science or Mathematics; strong communication.

RTL Design Engineer

Experience in RTL design and microarchitecture; proficient in Verilog/SystemVerilog; understanding of timing, synthesis, and EDA; strong problem-solving and collaboration.

Design Verification Engineer

Experience in design verification, system- and block-level verification, testbench development, UVM, Verilog/SystemVerilog; 3+ years; degree in EE or CS.

Architecture Modeling Engineer

Lead architecture modeling team; 5+ years as technical lead; 10+ years in modeling; degrees in ECE/CS; C++/SystemC proficiency.

Senior Analog Mixed-Signal Engineer

Analog Mixed-Signal Engineer

Senior-level analog/mixed-signal design experience; Cadence Virtuoso proficiency; Python/MATLAB modeling; SystemVerilog RNM; calibration/test algorithm development; cross-functional collaboration.

Title	Location	Date
Senior Test Engineer Full Time Bangalore, Karnataka, India · Onsite	Bangalore, Karnataka, India Onsite	Apr 20, 2026
Senior Product Engineer Full Time Bangalore, Karnataka, India · Onsite	Bangalore, Karnataka, India Onsite	Apr 20, 2026
Sr DFT Engineer Full Time · 3+ YOE Bangalore, Karnataka, India · Onsite	Bangalore, Karnataka, India Onsite	Feb 27, 2026
Sr Staff /Staff DFT Engineer Full Time · 8+ YOE Bangalore or Palo Alto or Austin · Onsite	Bangalore or Palo Alto or Austin Onsite	Feb 27, 2026
Senior Engineer: Physical Design Full Time · 3+ YOE Bangalore, Karnataka, India · Onsite	Bangalore, Karnataka, India Onsite	Feb 23, 2026
Senior Silicon Emulation Engineer Full Time · $120K-$225K · 3+ YOE Austin, Texas, United States · Hybrid	Austin, Texas, United States Hybrid	Jan 21, 2026
Director/Principal Engineer: Physical Design Full Time · 15+ YOE Bangalore, Karnataka, India · Remote	Bangalore, Karnataka, India Remote	Dec 16, 2025
Senior SoC RTL Design Engineer Full Time · 5+ YOE Bangalore, Karnataka, India · Onsite	Bangalore, Karnataka, India Onsite	Nov 19, 2025
Senior RTL Design Engineer Full Time · $120K-$225K · 8+ YOE Austin or Palo Alto · Hybrid	Austin or Palo Alto Hybrid	Oct 8, 2025
Senior Design Verification Engineer Full Time · $120K-$225K · 8+ YOE Austin or Palo Alto · Hybrid	Austin or Palo Alto Hybrid	Oct 8, 2025
Compiler Engineer - Algorithmic Workloads Compilation Full Time · 3+ YOE Austin or Palo Alto · Remote	Austin or Palo Alto Remote	Oct 3, 2025
Compiler Engineer – MLIR / PyTorch Infrastructure Full Time · 3+ YOE Austin or Palo Alto · Remote	Austin or Palo Alto Remote	Oct 3, 2025
Compiler Engineer - Machine Learning Compiler Full Time · 3+ YOE Austin or Palo Alto or United States · Remote	Austin or Palo Alto or United States Remote	Oct 3, 2025
AI Algorithms/Software Engineer Full Time · 5+ YOE Austin or Palo Alto or United States · Remote	Austin or Palo Alto or United States Remote	Oct 1, 2025
RTL Design Engineer Full Time · $120K-$225K · 3+ YOE Austin or Palo Alto · Hybrid	Austin or Palo Alto Hybrid	Sep 26, 2025
Design Verification Engineer Full Time · $120K-$225K · 3+ YOE Austin or Palo Alto · Hybrid	Austin or Palo Alto Hybrid	Sep 25, 2025
Architecture Modeling Engineer Full Time · 10+ YOE Austin or Redwood City · Hybrid	Austin or Redwood City Hybrid	Sep 3, 2025
Senior Analog Mixed-Signal Engineer Full Time United States · Remote	United States Remote	Jul 1, 2025

Activities	Semiconductor designArtificial intelligence processorsHardware engineeringEdge computing solutionsEmbedded systems development
Headquarters	US
Industries	SemiconductorsArtificial Intelligence
Name	Mythic
Employees	71
Type	Private
Tagline	Develops energy-efficient analog processors for AI inference.
Founded	2,012
Website	mythic.ai
Latest Funding Round	Series D
Latest Funding Year	2,025
Latest Funding Amount	125,000,000
Latest Investors	DCVC

Mythic

About Mythic