TetraMem

ASIC RTL/SoC Design Engineer

RTL/SoC Design Engineer

MS with 5+ years or PhD in Electrical Engineering; Verilog/SystemVerilog; VCS/Verdi; pre/post-layout simulation; AMBA APB/AXI; ARM core architectures; leadership in design.

CAD Engineer

10+ years CAD engineering in analog/digital IC design, strong EDA tool knowledge, UNIX, scripting (SKILL/TCL), 28nm node experience.

ASIC/SoC Design Verification Engineer

Design Verification Engineer

MS with 8+ years or PhD with 3+ years in EE/CE/CS; strong UVM/OVM; verification infra; Verilog/SystemVerilog; scripting; bus protocols; RTL and post-P&R; leadership.

Mid-Level Machine Learning Engineer

Machine Learning Engineer

5+ years ML experience; edge AI focus; ML frameworks PyTorch, TensorFlow, JAX; C/C++, Python; ability to work independently in fast-paced startup.

Application Engineer

Provide technical support and integration for AI in-memory computing software; strong problem-solving; MS with 5+ years or PhD; startup-friendly; sales/marketing experience preferred.

Analog/Mixed-Signal IC Design Engineer

MS or PhD in Electrical Engineering; 5+ years analog/mixed-signal IC design; CMOS processes; tape-out experience; strong CAD/EDA skills; layout, verification; startup capable.

Analog Layout Engineer

8+ years in analog/mixed-signal layout design; deep submicron CMOS; Cadence Virtuoso, Calibre DRC/LVS; strong leadership and collaboration.

Analog/Mixed-Signal Verification Engineer SG

Analog/Mixed-Signal Verification Engineer

BS EE with 5+ years in analog/mixed-signal verification; strong testbench design, verification tooling, and scripting in Python/Perl/C; good debugging and collaboration.

Bachelor's in Electrical Engineering with 5+ years of related experience; strong analog/mixed-signal verification; Verilog/SystemVerilog; SPICE; scripting in Perl/Python/C; testplan development; ability to work with cross-functional teams.

ASIC RTL/SoC Design Engineer SG

Lead RTL/SoC design, verification, and collaboration with backend; strong experience in RTL, IP integration, and PPA optimization.

ASIC Design Verification Engineer

MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.

Memory Circuit Design Engineer

MS or PhD in Electrical Engineering with 5+ years of experience in circuit design in advanced CMOS processes.

ASIC Design Engineer

MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design. Experience with Verilog, VCS, and pre/post-layout simulation.

Analog/Mixed-Signal IC Verification Engineer

IC Verification Engineer

B.S. EE and 7+ years of relevant industry experience or equivalent; strong understanding of analog and mixed-signal circuit design and verification principles.

ASIC RTL Design Engineer

MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design.

Title	Location	Date
ASIC RTL/SoC Design Engineer Full Time · $110K-$300K · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Mar 10, 2025
CAD Engineer Full Time · $110K-$300K · 10+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Mar 10, 2025
ASIC/SoC Design Verification Engineer Full Time · $110K-$300K · 8+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Mar 10, 2025
Mid-Level Machine Learning Engineer Full Time · $110K-$300K · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Mar 10, 2025
Application Engineer Full Time · $110K-$300K · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Dec 27, 2024
Analog/Mixed-Signal IC Design Engineer Full Time · $110K-$300K · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Dec 18, 2024
Analog Layout Engineer Full Time · $110K-$300K · 8+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Dec 18, 2024
Analog/Mixed-Signal Verification Engineer SG Full Time · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Dec 18, 2024
Analog/Mixed-Signal Verification Engineer Full Time · $110K-$300K · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Dec 18, 2024
ASIC RTL/SoC Design Engineer SG Full Time · $80K-$180K · 5+ YOE Singapore · Onsite	Singapore Onsite	Dec 18, 2024
ASIC/SoC Design Verification Engineer Full Time · 8+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Nov 28, 2023
Memory Circuit Design Engineer Full Time · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Nov 21, 2023
ASIC RTL/SoC Design Engineer Full Time · 5+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Nov 21, 2023
Analog/Mixed-Signal IC Verification Engineer Full Time · 7+ YOE Fremont, California, United States · Onsite	Fremont, California, United States Onsite	Nov 21, 2023
ASIC Design Verification Engineer Full Time · 8+ YOE Singapore, Singapore · Onsite	Singapore, Singapore Onsite	Nov 2, 2022
ASIC RTL Design Engineer Full Time · 5+ YOE Singapore, Singapore · Onsite	Singapore, Singapore Onsite	Nov 2, 2022

Activities	Designing AI acceleratorsDeveloping in-memory computing hardwareManufacturing neural processing unitsProviding edge AI inference chipsDeveloping resistive RAM technology
Headquarters	US
Industries	SemiconductorsArtificial Intelligence
Name	TetraMem
Employees	73
Type	Private
Tagline	Designing in-memory computing chips for edge AI applications.
Founded	2,018
Website	tetramem.com
Latest Funding Round	Corporate Round
Latest Funding Year	2,025
Latest Funding Amount	72,000,000
Latest Investors	SK Square

TetraMem

About TetraMem