Explore 4 optimization algorithm developer jobs from 3 hiring companies in Horseshoe Bay, TX, US. Filter by remote, salary, experience, and company, then open any listing to apply.

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Optimization Algorithm Developer

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Optimization Algorithm Developer Jobs

NVIDIA

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Firefly Aerospace

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Flight Dynamics Engineer III Trajectory Elytra - Careers At Firefly Aerospace	

	

	

	


	
	
	

	
	
	

		 							
	 
		
	
	
	
	
	
	













						
				
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										<p>Career Opportunities with Firefly Aerospace</p>
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		<h2>Flight Dynamics Engineer III (Trajectory), Elytra</h2>	
	
	
			
		
		      			      	<b>Department:</b>
					Aerospace Software Engineering		      					
		      			      	<b>Location:</b>
					Cedar Park, TX<br />					
		      		      		      		      		      		      		



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		<div><p><a><strong>ABOUT FIREFLY AEROSPACE </strong></a></p>

<p>Firefly Aerospace is a space and defense technology company that enables our world to launch, land, and operate in space � anywhere, anytime. As the partner of choice for critical space missions, Firefly is the only commercial company to launch a satellite to orbit with 24-hour notice and the only company to achieve a successful Moon landing. Our launch vehicles, lunar landers, and orbital vehicles provide government and commercial customers with full mission services from low Earth orbit to the Moon and beyond. Headquartered in north Austin, Texas, Firefly is looking for passionate, hardworking innovators to join our team and help fuel our successful trajectory into space. </p>

<h1><strong>SUMMARY</strong></h1>

<p>As a Senior Flight Dynamics Engineer specializing in trajectory and maneuver design at Firefly, you will design and optimize spacecraft trajectories and maneuver sequences for operational missions spanning LEO and cislunar space. In this role, you will develop targeting algorithms, create error budgets, and serve as a flight dynamics operator while collaborating with cross-functional teams to translate mission designs into executable operations. This position combines advanced mission design with hands-on operational support while mentoring junior engineers in a fast-paced, mission-critical environment.</p>

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<h1><strong>RESPONSIBILITIES</strong></h1>

<ul>
	<li>Optimize spacecraft trajectories to satisfy mission requirements while balancing delta-V budgets, mission duration, and payload constraints</li>
	<li>Design and maintain mission designs from the conceptual phase through the end of spacecraft mission operations</li>
	<li>Develop algorithms to target maneuvers that achieve spacecraft mission objectives</li>
	<li>Create maneuver error budgets and perform sensitivity analysis to assess robustness to execution uncertainties</li>
	<li>Formulate and analyze contingency maneuver plans and abort scenarios for off-nominal conditions</li>
	<li>Interface with cross-discipline teams to translate maneuver plans into executable command sequences and operational procedures</li>
	<li>Serve as a flight dynamics operator for spacecraft missions and perform maneuver reconstruction to improve spacecraft models</li>
	<li>Perform verification and validation of flight dynamics models and software using analytical solutions, benchmarks, flight data, and unit tests</li>
	<li>Author technical documentation and analysis reports that communicate flight dynamics concepts and results to diverse audiences</li>
</ul>

<h1><strong>QUALIFICATIONS</strong></h1>

<h2>Required</h2>

<ul>
	<li>Bachelor's degree in aerospace engineering, physics, mathematics, or related field</li>
	<li>5-8 years of experience in spacecraft flight dynamics with significant depth in mission design or maneuver planning</li>
	<li>Experience supporting operational spacecraft missions through multiple mission phases</li>
	<li>Advanced understanding of orbital mechanics theory and applications</li>
	<li>Understanding of spacecraft attitude control and its impact on maneuver execution accuracy</li>
	<li>Strong understanding of targeting and optimization methods</li>
	<li>Knowledge of estimation theory and uncertainty modeling</li>
	<li>Experience in software development and modeling/simulation for spaceflight applications</li>
	<li>Working knowledge of Python and Linux</li>
	<li>Proficiency with one or more commercial trajectory design software tools (STK, FreeFlyer, GMAT, or similar)</li>
	<li>Excellent communication and presentation skills</li>
</ul>

<h2>Desired</h2>

<ul>
	<li>Advanced degree (master's or PhD) in aerospace engineering, physics, mathematics, or related field</li>
	<li>Expert-level proficiency in STK for spacecraft trajectory design</li>
	<li>Python proficiency and experience with JPL's MONTE software suite</li>
	<li>Software engineering expertise including skills in version control (Git), code review, automated testing, documentation, and CI/CD workflows</li>
	<li>Comprehensive knowledge of spacecraft subsystems and their impact on trajectory design and maneuver planning</li>
	<li>Proven ability to mentor and develop junior engineers while managing technical responsibilities</li>
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<p><strong>Firefly offers outstanding benefits for our employees, including generous health, dental and vision plans with low plan deductibles, parental leave, educational reimbursement, short term disability, and flexible PTO options.</strong></p>

<p><em>To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. </em></p>

<p><em>Firefly Aerospace, Inc. is an Equal Opportunity Employer; employment with Firefly is governed based on merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.</em></p>
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Flight Dynamics Engineer III (Trajectory), Elytra

Flight Dynamics Engineer

Design and optimize spacecraft trajectories and maneuver sequences; develop targeting algorithms; support operational missions; mentor engineers.

<p>Are you passionate about crafting solutions to intricate challenges? Join the Low Power group<br />at Silicon Technologies and contribute to the development of cutting-edge technology and<br />capabilities for low-power chip design. Your work will fuel Apple’s next-generation chips!<br />Responsible for developing and improving low-power flow algorithms using AI and machine<br />learning, which significantly impacts the work of many designers involved in mobile system-on-<br />chips</p><h3>Description</h3><p>In this role, you’ll develop innovative automated tools and capabilities for the Silicon<br />Engineering Power team. Your contributions will enable the creation of chips with<br />unprecedented power eﬃciency. You’ll be involved in the architecture, implementation, and<br />validation of advanced low-power design and verification workflows. Additionally, you’ll shape<br />low-power strategies for emerging technologies.<br />Your responsibilities will encompass the development of flows and tools for power analysis,<br />optimization, and verification, seamlessly integrated into stages such as RTL development/<br />verification, synthesis, or place-and-route (P&amp;R). You’ll actively leverage various AI tools to<br />innovate new solutions and enhance existing ones. Additionally, you’ll collaborate with design<br />teams to address queries, resolve issues, and ensure the smooth adoption of these<br />methodologies.</p><h3>Minimum Qualifications</h3><ul><li>Minimum requirement of a Bachelors Degree in a relevant field</li></ul><h3>Preferred Qualifications</h3><ul><li>Solid grasp of VLSI designs and SOC design processes.</li><li>Enthusiasm for scripting and leveraging low-power expertise to innovate software solutions.</li><li>Enthusiasm for leveraging AI/ML to innovate low-power methodologies and flows.</li><li>Experience in flow development and algorithm design using Python/Perl/TCL.</li><li>Demonstrated proficiency in contemporary software testing and development methodologies.</li><li>Familiarity with low-power principles (e.g., low-power design techniques) is advantageous.</li></ul>

SoC Power Flow Methodology Engineer

Develop and improve low-power flow algorithms using AI/ML; build tools for power analysis, optimization, and verification across RTL to P&R

<p>NVIDIA&#39;s success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a Senior R&amp;D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.). Understanding both software and hardware aspects is the key. Creativity and self-drive to explore and perfect fast, high-capacity software is required. If you like to work across many technical areas and see your successes directly realized in the world&#39;s best AI hardware, it does not get any better than this!</p><p></p><p>Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We&#39;re not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles.</p><p></p><p><b>What you’ll be doing:</b></p><ul><li><p>Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry&#39;s alternatives in high capacity timing closure and will advance even further with your contributions.</p></li><li><p>Improve algorithms (in C&#43;&#43;) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.</p></li><li><p>As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.</p></li></ul><p></p><p><b>What we need to see:</b></p><ul><li><p>BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science</p></li><li><p>6&#43; years in VLSI algorithms development using C&#43;&#43;</p></li><li><p>Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.</p></li><li><p>Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python</p></li><li><p>Strong communication and interpersonal skills</p></li></ul><p></p><p><b>Ways to stand out from the crowd:</b></p><ul><li><p>C&#43;&#43;14 or newer experience, such as lambdas and concurrency</p></li><li><p>Detailed understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA</p></li><li><p>Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.</p></li><li><p>Highly driven to craft outstanding software towards improving PPA with a dedication to continuous improvement</p></li><li><p>Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design</p></li></ul><p></p><p>NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!</p><p style="text-align:inherit"></p><p style="text-align:inherit"></p>Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD.<div><div><div><div><div><div><div><p></p><p><span>You will also be eligible for equity and <a href="https://www.nvidia.com/en-us/benefits/" target="_blank">benefits</a>.</span></p><p></p></div></div></div></div></div></div></div>Applications for this job will be accepted at least until March 26, 2026.<p></p><p>This posting is for an existing vacancy. </p><p>NVIDIA uses AI tools in its recruiting processes.</p><p></p>NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.<p style="text-align:inherit"></p><p style="text-align:inherit"></p>

Senior Software R&D Engineer, VLSI Physical Design

Senior Software R&D Engineer

BS/MS/PhD in EE or CS; 6+ years VLSI algorithms in C++; strong VLSI timing optimization knowledge; experience with ICC2, Innovus, PrimeTime, Tempus, StarRC; proficiency in Perl, Tcl, Python; strong communication.

<p>NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.</p><p></p><p>Come join the team and see how you can make a lasting impact on the world. We are looking for an AI &amp; Deep Learning Compiler Engineer. NVIDIA is hiring software engineers for its Deep Learning &amp; AI Compiler (DLC) team. Academic and commercial groups around the world are using GPUs to power a revolution in deep learning, enabling breakthroughs in many areas, e.g. large language models, generative AI, recommendation systems, image classification, speech recognition, etc. With the rapid advancement of AI, our DLC has been the backbone of NVIDIA’s inference engine, spanning across data centers, personal devices, automotive, and robotics. The compiler must deliver leading inference performance, fast build time, reduced memory footprints, and ease of use in the forms of both Ahead-of-Time and Just-in-Time. Join the team building the DLC which will be used by the entire deep learning community.</p><p></p><p><b>What you&#39;ll be doing:</b></p><ul><li><p>Analyzing deep learning networks and developing compiler optimization algorithms.</p></li><li><p>Strong programming skills in CUDA including analyzing and debugging performance bottlenecks on GPUs</p></li><li><p>Scope of these efforts includes defining public APIs, performance optimizations and analysis, crafting and implementing compiler techniques for AI workloads and future NVIDIA GPUs.</p></li></ul><p></p><p><b>What we need to see:</b></p><ul><li><p>Bachelor’s, master’s or Ph.D. in Computer Science, Computer Engineering, related field or equivalent experience.</p></li><li><p>3&#43; years of relevant work or research experience in performance analysis and compiler optimizations.</p></li><li><p>Experience with compiler technologies (e.g., MLIR, LLVM, XLA, Triton, etc.).</p></li><li><p>Excellent C/C&#43;&#43; and Python programming and software design skills, including debugging, performance analysis, and test design.</p></li><li><p>Ability to work independently, define project goals and scope, and lead your own development efforts.</p></li><li><p>Strong interpersonal skills are required along with the ability to work in a dynamic product-oriented team.</p></li></ul><p></p><p><b>Ways to stand out from the crowd:</b></p><ul><li><p>Proficient in CPU and/or GPU architecture especially modern Nvidia GPUs like Hopper and Blackwell</p></li><li><p>Understanding of deep learning models, algorithms, and frameworks, such as PyTorch, JAX.</p></li><li><p>GPU kernel authoring and performance analysis using tools such as Nsight Compute.</p></li><li><p>A track record of success in mentoring early-career engineers and interns is a bonus.</p></li><li><p>Track record on new hardware bring-up is a plus.</p></li></ul><p></p><p>With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology industry&#39;s most desirable employers. We have some of the most brilliant and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state of the art fields such as Virtual Reality, Artificial Intelligence, Deep Learning and Autonomous Vehicles.<span>​</span></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p>Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD.<div><div><div><div><div><div><div><p></p><p><span>You will also be eligible for equity and <a href="https://www.nvidia.com/en-us/benefits/" target="_blank">benefits</a>.</span></p><p></p></div></div></div></div></div></div></div>Applications for this job will be accepted at least until May 4, 2026.<p></p><p>This posting is for an existing vacancy. </p><p>NVIDIA uses AI tools in its recruiting processes.</p><p></p>NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.<p style="text-align:inherit"></p><p style="text-align:inherit"></p>

Senior AI Compiler Engineer, Algorithms and Code-Generation

AI Compiler Engineer

Bachelor’s/Master’s/Ph.D. in CS/CE or related field; 3+ years in performance analysis and compiler optimizations; experience with MLIR/LLVM/XLA/Triton; strong C/C++ and Python; independent and collaborative; good communication.

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