Explore 3 optimization algorithm developer jobs from 2 hiring companies in New Braunfels, TX, US. Filter by remote, salary, experience, and company, then open any listing to apply.

optimization-algorithm-developer

Optimization Algorithm Developer

San Antonio

Cibolo

Schertz

Seguin

Canyon Lake

Universal City

San Marcos

Austin

Live Oak

Converse

Selma

Kyle

Timberwood Park

Lockhart

Buda

Lake Dunlap

Boerne

Leon Valley

Garden Ridge

Optimization Algorithm Developer Jobs

NVIDIA

Apple

Onsite

Hybrid

Are you passionate about crafting solutions to intricate challenges? Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple’s next-generation chips! Responsible for developing and improving low-power flow algorithms using AI and machine learning, which significantly impacts the work of many designers involved in mobile system-on- chips<h3>Description</h3>In this role, you’ll develop innovative automated tools and capabilities for the Silicon Engineering Power team. Your contributions will enable the creation of chips with unprecedented power eﬃciency. You’ll be involved in the architecture, implementation, and validation of advanced low-power design and verification workflows. Additionally, you’ll shape low-power strategies for emerging technologies. Your responsibilities will encompass the development of flows and tools for power analysis, optimization, and verification, seamlessly integrated into stages such as RTL development/ verification, synthesis, or place-and-route (P&amp;R). You’ll actively leverage various AI tools to innovate new solutions and enhance existing ones. Additionally, you’ll collaborate with design teams to address queries, resolve issues, and ensure the smooth adoption of these methodologies.<h3>Minimum Qualifications</h3><ul><li>Minimum requirement of a Bachelors Degree in a relevant field</li></ul><h3>Preferred Qualifications</h3><ul><li>Solid grasp of VLSI designs and SOC design processes.</li><li>Enthusiasm for scripting and leveraging low-power expertise to innovate software solutions.</li><li>Enthusiasm for leveraging AI/ML to innovate low-power methodologies and flows.</li><li>Experience in flow development and algorithm design using Python/Perl/TCL.</li><li>Demonstrated proficiency in contemporary software testing and development methodologies.</li><li>Familiarity with low-power principles (e.g., low-power design techniques) is advantageous.</li></ul>

SoC Power Flow Methodology Engineer

Develop and improve low-power flow algorithms using AI/ML; build tools for power analysis, optimization, and verification across RTL to P&R

NVIDIA&#39;s success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a Senior R&amp;D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.). Understanding both software and hardware aspects is the key. Creativity and self-drive to explore and perfect fast, high-capacity software is required. If you like to work across many technical areas and see your successes directly realized in the world&#39;s best AI hardware, it does not get any better than this!Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We&#39;re not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles.What you’ll be doing:<ul><li>Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry&#39;s alternatives in high capacity timing closure and will advance even further with your contributions.</li><li>Improve algorithms (in C&#43;&#43;) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.</li><li>As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.</li></ul>What we need to see:<ul><li>BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science</li><li>6&#43; years in VLSI algorithms development using C&#43;&#43;</li><li>Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.</li><li>Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python</li><li>Strong communication and interpersonal skills</li></ul>Ways to stand out from the crowd:<ul><li>C&#43;&#43;14 or newer experience, such as lambdas and concurrency</li><li>Detailed understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA</li><li>Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.</li><li>Highly driven to craft outstanding software towards improving PPA with a dedication to continuous improvement</li><li>Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design</li></ul>NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD.<div><div><div><div><div><div><div>You will also be eligible for equity and <a href="https://www.nvidia.com/en-us/benefits/" target="_blank">benefits</a>.</div></div></div></div></div></div></div>Applications for this job will be accepted at least until March 26, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Senior Software R&D Engineer, VLSI Physical Design

Senior Software R&D Engineer

BS/MS/PhD in EE or CS; 6+ years VLSI algorithms in C++; strong VLSI timing optimization knowledge; experience with ICC2, Innovus, PrimeTime, Tempus, StarRC; proficiency in Perl, Tcl, Python; strong communication.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.Come join the team and see how you can make a lasting impact on the world. We are looking for an AI &amp; Deep Learning Compiler Engineer. NVIDIA is hiring software engineers for its Deep Learning &amp; AI Compiler (DLC) team. Academic and commercial groups around the world are using GPUs to power a revolution in deep learning, enabling breakthroughs in many areas, e.g. large language models, generative AI, recommendation systems, image classification, speech recognition, etc. With the rapid advancement of AI, our DLC has been the backbone of NVIDIA’s inference engine, spanning across data centers, personal devices, automotive, and robotics. The compiler must deliver leading inference performance, fast build time, reduced memory footprints, and ease of use in the forms of both Ahead-of-Time and Just-in-Time. Join the team building the DLC which will be used by the entire deep learning community.What you&#39;ll be doing:<ul><li>Analyzing deep learning networks and developing compiler optimization algorithms.</li><li>Strong programming skills in CUDA including analyzing and debugging performance bottlenecks on GPUs</li><li>Scope of these efforts includes defining public APIs, performance optimizations and analysis, crafting and implementing compiler techniques for AI workloads and future NVIDIA GPUs.</li></ul>What we need to see:<ul><li>Bachelor’s, master’s or Ph.D. in Computer Science, Computer Engineering, related field or equivalent experience.</li><li>3&#43; years of relevant work or research experience in performance analysis and compiler optimizations.</li><li>Experience with compiler technologies (e.g., MLIR, LLVM, XLA, Triton, etc.).</li><li>Excellent C/C&#43;&#43; and Python programming and software design skills, including debugging, performance analysis, and test design.</li><li>Ability to work independently, define project goals and scope, and lead your own development efforts.</li><li>Strong interpersonal skills are required along with the ability to work in a dynamic product-oriented team.</li></ul>Ways to stand out from the crowd:<ul><li>Proficient in CPU and/or GPU architecture especially modern Nvidia GPUs like Hopper and Blackwell</li><li>Understanding of deep learning models, algorithms, and frameworks, such as PyTorch, JAX.</li><li>GPU kernel authoring and performance analysis using tools such as Nsight Compute.</li><li>A track record of success in mentoring early-career engineers and interns is a bonus.</li><li>Track record on new hardware bring-up is a plus.</li></ul>With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology industry&#39;s most desirable employers. We have some of the most brilliant and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state of the art fields such as Virtual Reality, Artificial Intelligence, Deep Learning and Autonomous Vehicles.​Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD.<div><div><div><div><div><div><div>You will also be eligible for equity and <a href="https://www.nvidia.com/en-us/benefits/" target="_blank">benefits</a>.</div></div></div></div></div></div></div>Applications for this job will be accepted at least until May 4, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Senior AI Compiler Engineer, Algorithms and Code-Generation

AI Compiler Engineer

Bachelor’s/Master’s/Ph.D. in CS/CE or related field; 3+ years in performance analysis and compiler optimizations; experience with MLIR/LLVM/XLA/Triton; strong C/C++ and Python; independent and collaborative; good communication.

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Optimization Algorithm Developer Jobs in New Braunfels, TX, US

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