Explore 3 optimization algorithm developer jobs from 3 hiring companies in Templeton, MA, US. Filter by remote, salary, experience, and company, then open any listing to apply.

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Optimization Algorithm Developer

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Optimization Algorithm Developer Jobs

Apple

Mitsubishi Electric Research Laboratories

Synopsys

Onsite

Hybrid

AI augmented optimization - Careers At Mitsubishi Electric Research Laboratories	

	

	

	


	
	
	

	
	
	

		 							
	 
		
	
	
	
	
	
	













						
				
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										<p>Career Opportunities with Mitsubishi Electric Research Laboratories</p>
<p><em>A great place to work.</em></p>
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				<div>Careers At Mitsubishi Electric Research Laboratories</div>								
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		<h2>AI augmented optimization</h2>	
	
	
			
		
		      			      	<b>Department:</b>
					OR Interns		      					
		      			      	<b>Location:</b>
					Cambridge, MA<br />					
		      		      		      		      		      		      		



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		<div><p>We seek a talented individual for a joint research project in AI-augmented optimization: Using LLMs and related technologies to aid in the formulation, transformation, and accelerated solution of typical Operations Research optimization problems.  Depending on intern skill set, the project may also consider post-optimization enhancements � explanation, robustification, and generation of alternatives.  The ideal applicant will have technical background and research experience on both sides (AI & OR) of the project, including familiarity with software environments used to do machine learning & mathematical programming.  The internship has flexible dates in 2026. </p>

<p><strong>The strongest candidates will have:</strong></p>

<ul>
	<li>A solid background in machine learning, linear algebra, convex optimization, algorithm analysis, computational geometry.</li>
	<li>Experience with Mixed-Integer Programs (linear, nonlinear, nonconvex)</li>
	<li>Experience deploying and fine-tuning LLM-type AI systems.</li>
	<li>Competence with related software packages such as Gurobi, CVX, PyOpt, PyTorch, etc.</li>
	<li>Fluency in python.</li>
	<li>Interest (& experience) in publishing in top-tier venues.</li>
</ul>

<p>The pay range for this internship position will be 6-8K per month.</p>


<p><em>Mitsubishi Electric Research Labs, Inc. "MERL" provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, national origin, age, disability or genetics. In addition to federal law requirements, MERL complies with applicable state and local laws governing nondiscrimination in employment in every location in which the company has facilities. This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation and training.</em></p>

<p><em>MERL expressly prohibits any form of workplace harassment based on race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, genetic information, disability, or veteran status. Improper interference with the ability of MERL�s employees to perform their job duties may result in discipline up to and including discharge.</em></p>

<p><em>Working at MERL requires full authorization to work in the U.S and access to technology, software and other information that is subject to governmental access control restrictions, due to export controls. Employment is conditioned on continued full authorization to work in the U.S and the availability of government authorization for the release of these items, which might include without limitation, obtaining an export license or other documentation. MERL may delay commencement of employment, rescind an offer of employment, terminate employment, and/or modify job responsibilities, compensation, benefits, and/or access to MERL facilities and information systems, as MERL deems appropriate, to ensure practical compliance with applicable employment law and government access control restrictions. </em></p>

<p><em>In addition to base pay, interns receive a relocation stipend, covered travel to and from MERL, and a monthly Charlie Card for local commuting. Interns are invited to participate in weekly social gatherings and professional development opportunities, including research talks by both internal and external speakers. Interns who meet the 90-day waiting period are also eligible for health insurance coverage. MERL provides immigration support for qualified candidates as needed. Employment is considered �at-will,� and the Company reserves the right to modify base salary or any other compensation program at any time, including for reasons related to individual performance, departmental or Company performance, and market conditions.</em></p>
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AI augmented optimization

AI augmented optimization intern

Internship in AI-augmented optimization; background in ML, linear algebra, convex optimization, algorithm analysis, computational geometry; experience with MIP, LLM deployment; familiarity with Gurobi, CVX, PyOpt, PyTorch; fluent in Python; interest in publishing.

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:
You are an inventive and detail-oriented engineer with a passion for solving complex technical challenges at the intersection of hardware and software. You thrive in environments where algorithmic excellence and scalable solutions are paramount. Your deep understanding of object-oriented programming and data structures enables you to architect robust software systems that handle massive hardware designs with efficiency and precision. You are energized by the prospect of working with multi-billion-gate processor descriptions, and possess the analytical acumen to optimize performance, scalability, and reliability. Collaboration is second nature to you; you build strong relationships with cross-functional teams, including hardware architects and performance engineers, to tackle intricate compilation and placement problems. Your commitment to continuous improvement drives you to refine algorithms, flows, and infrastructure, ensuring that the ZeBu emulation platform stays at the forefront of industry innovation. You approach every challenge with curiosity, resilience, and a growth mindset, and are eager to shape the future of chip verification technology for leading semiconductor companies. You value diversity, inclusion, and teamwork, recognizing that the best solutions emerge from a blend of perspectives and experiences. If you are ready to make a tangible impact in a dynamic, innovation-driven environment, Synopsys offers you the opportunity to excel.

What You’ll Be Doing:
Design, implement, and optimize compilation algorithms for mapping large-scale processor hardware descriptions onto the ZeBu emulator
Develop scalable solutions to handle multi-billion-gate designs within tight runtime and memory constraints
Apply advanced problem-solving skills to debug complex compilation, placement, and performance issues
Develop and maintain high-quality, modular, and extensible object-oriented software in C++
Collaborate closely with hardware architects, performance engineers, and emulator platform teams to ensure seamless integration and performance
Contribute to continuous improvement of compilation flows, algorithms, and infrastructure for enhanced efficiency and robustness
Participate in code reviews, design discussions, and knowledge sharing sessions with the broader engineering community

The Impact You Will Have:
Enable leading semiconductor companies to verify next-generation processor designs before commercialization
Drive performance and scalability improvements, reducing compile and placement times for massive hardware designs
Advance state-of-the-art compilation technologies in emulation, directly shaping the future of chip verification
Enhance robustness and reliability of the ZeBu emulation platform, ensuring successful deployment in real-world scenarios
Foster innovation and collaboration within the ZeBu Compiler Team and across Synopsys engineering groups
Support industry leaders in achieving faster time-to-market for their products through efficient emulation workflows
Champion best practices in software engineering, contributing to the overall quality and maintainability of the codebase

What You’ll Need:
3-5 years of relevant experience 
Strong skills in problem solving and algorithmic thinking, with proven experience in tackling challenging technical problems
Solid expertise in object-oriented programming (preferably C++)
Deep understanding of data structures and algorithms, with the ability to design efficient and scalable solutions
Experience working with complex systems and large codebases
Strong analytical skills and meticulous attention to detail
Exposure to performance optimization, memory efficiency, or parallel computing (preferred)
Familiarity with hardware description languages (Verilog, SystemVerilog, VHDL) (preferred)
Experience with emulation, FPGA, EDA tools, or large-scale system software (preferred)

Who You Are:
Collaborative team player who values diversity and inclusion
Innovative thinker with a passion for continuous learning and improvement
Resilient problem solver who thrives in fast-paced, challenge-driven environments
Excellent communicator, able to articulate complex technical concepts clearly
Detail-oriented, organized, and committed to high-quality deliverables
Self-motivated and adaptable, with a growth mindset

The Team You’ll Be A Part Of:
You’ll join the ZeBu Compiler Team—a group of passionate engineers dedicated to advancing emulation technology for the world’s leading semiconductor companies. The team focuses on developing innovative compilation algorithms, scalable software solutions, and robust infrastructure to enable efficient verification of massive hardware designs. Collaboration, knowledge sharing, and a commitment to excellence define the team’s culture, empowering each member to make a meaningful impact.

Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

R&D Engineering, Staff Engineer-16559

Staff Engineer

3-5 years of relevant experience; strong problem-solving and algorithmic skills; proficient in object-oriented programming (C++); knowledge of data structures and algorithms; experience with large codebases and performance optimization; familiarity with hardware description languages and emulation tools.

<p>Apple’s RF System Engineering team is seeking a motivated and dedicated expert to define the next generation of Cellular RF Receiver architectures. In this role, you will architect and deliver groundbreaking wireless solutions for future Apple products, working on today's 5G New Radio and blazing the path to 6G. You will have a unique opportunity to develop the core technologies that enable an outstanding wireless experience for millions of customers worldwide.</p><h3>Description</h3><p>In this role, you will drive the control architecture and algorithms for the RF receiver, collaborating across systems engineering, RF circuit design, digital implementation, platform architecture, software engineering, and production teams to define and deliver solutions that push the boundaries of performance, quality, and implementation efficiency.</p><h3>Minimum Qualifications</h3><ul><li>BSEE required.</li><li>Understanding of Cellular Radio/3GPP Standards (UMTS, LTE, 5G NR FR1/2) and familiarity with emerging 6G research directions.</li><li>Knowledge of RF receiver architectures from antenna to analog/digital base band processing including a comprehensive understanding of RF circuit impairments and their impact on system performance.</li><li>Good overview of cellular system use cases and RF/baseband interactions and procedures.</li><li>Proficiency in hardware/software co-design and a comprehensive grasp of the trade-offs inherent in digital hardware and software/firmware implementations.</li><li>Expert-level proficiency in Python or C++ is required.</li><li>Experience applying Artificial Intelligence (AI) or Machine Learning (ML) to improve multi-objective optimizations and accelerate engineering workflows.</li><li>Excellent analytical and problem-solving skills, with the ability to collaborate effectively in a global, multi-disciplinary team.</li></ul><h3>Preferred Qualifications</h3><ul><li>Expertise in microcontroller architectures used for real time operation and how to program them.</li><li>Proficiency in AI/ML native applications, with experience utilizing tools such as TensorFlow or PyTorch.</li><li>Knowledge of cellular modem architectures including their associated concepts and algorithms.</li><li>PhD degree with education focus in RF, especially on cellular receiver architectures.</li><li>System Engineering experience with a deep background in DSP for wireless communication systems. Experience in refining from abstract definition towards bit true reference models.</li><li>Proficiency in mathematical modeling and analysis, with the ability to build abstract system models leveraging control theory for understanding and designing control and closed-loop feedback systems, optimization theory for multi-objective trade-space analysis and statistical methods for performance modeling under uncertainty.</li></ul>

Cellular RF Receiver Algorithms Systems Engineer

BSEE; strong knowledge of cellular standards (UMTS, LTE, 5G NR FR1/2) and RF receiver architectures; Python or C++ proficiency; AI/ML experience for optimization; excellent problem-solving and cross‑functional collaboration.

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