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Viasat

Hybrid

Onsite

CSS is seeking five (5) experienced Journeyman Computer Programmers to support the maintenance, development, and modernization of DRAS at DFAS. DRAS is an IBM z/OS mainframe system comprising the Retired and Casualty Pay System (RCPS), Annuity Pay System (APS), and Combat Related Special Compensation (CRSC), collectively processing approximately $6 billion per month for 2.5 million military retirees and beneficiaries. Team members will operate under the direction of the Technical Lead Programmer and execute the full software development lifecycle including requirements analysis, coding, unit testing, peer review, code turnover, and production support.
 
Key Responsibilities
Software Development & Unit Testing
<ul>
<li>Develop and maintain COBOL programs for z/OS mainframe environments, meeting all SCR specifications and DRAS design documentation requirements, free of defects.</li>
<li>Write and execute JCL, CICS transactions, and SQL queries as required; utilize ADS-Online, ADS-Batch, and MQ Series as directed.</li>
<li>Perform unit testing of Configuration Items (CIs) to confirm correct functionality; complete and document test results in compliance with DFAS business processes.</li>
<li>Upon successful test completion, move code into designated staging areas and notify appropriate parties for production deployment.</li>
<li>Ensure all code complies with DRAS-defined coding standards, industry best practices, and DFAS CMM Level 3 requirements.</li>
</ul>
Requirements Analysis
<ul>
<li>Review SCRs, white papers, email requests, and meeting action items from R&A Operations and other sources.</li>
<li>Contribute to written impact analyses of proposed changes, identifying affected system components and providing rough order of magnitude (ROM) estimates with +/- 15% accuracy for staff-hours and calendar days.</li>
<li>Execute data queries to identify data conditions relevant to detailed requirements reviews.</li>
<li>Participate in user needs analysis, system analysis and design, and technical documentation activities.</li>
</ul>
Code Turnover & Peer Review
<ul>
<li>Participate in code walkthroughs, reviewing all testing plans and results to confirm required testing is complete and all defects are identified.</li>
<li>Participate in Peer Review meetings; present and receive feedback on defects, code efficiency, and conformance with coding standards.</li>
<li>Maintain 95% monthly attendance at all required peer review and team meetings.</li>
</ul>
Production Support
<ul>
<li>Provide production support to research and resolve issues affecting DRAS payroll processing (RCPS, APS, CRSC).</li>
<li>Monitor production performance and job execution; document 100% of reported issues in accordance with DFAS business processes.</li>
<li>Participate in ad hoc user meetings to assist in resolving application issues as directed by the Technical Lead or COR.</li>
</ul>
SDLC & Process Compliance
<ul>
<li>Comply with DFAS-defined timeframes for program analysis, programming, unit testing, and pre-implementation support within the DRAS SDLC.</li>
<li>Participate in system requirements reviews, critical design reviews, test readiness reviews, and post-implementation reviews.</li>
<li>Participate in the DRAS Agile transformation effort; attend DFAS-sponsored Agile Boot Camp training and meet defined maturity expectations during the transition.</li>
<li>Maintain regular attendance at team meetings; actively contribute to team standup and planning sessions.</li>
</ul>
Training & Security Compliance
<ul>
<li>Complete all required DoD mandatory training within 30 days of CAC receipt: Cyber Awareness Challenge, CUI Training, Antiterrorism Level I, Insider Threat Awareness, Privacy Act, Records Management, and Unauthorized Disclosure of Classified Information.</li>
<li>Renew all mandatory training modules annually to maintain DFAS network and system access.</li>
<li>Adhere to all DFAS security requirements including physical security, information security, CAC usage, and CUI handling policies.</li>
<li>Immediately report any security incidents or violations to the contractor FSO, DFAS Manager, CO, COR, Director of Force Protection, and DFAS Personnel Security.</li>
</ul>
 
Required Qualifications
<ul>
<li>Bachelor's degree in Computer Science, Information Technology, or related field; or equivalent combination of education and directly applicable mainframe development experience.</li>
<li>Minimum 5 years of hands-on IBM mainframe programming experience with COBOL for z/OS as the primary language.</li>
<li>Working proficiency in JCL, CICS, and z/OS 2.1 operating environment.</li>
<li>Experience with VSAM file structures and at least one of: DB2, IDMS.</li>
<li>Familiarity with TSO, ROSCOE, and common mainframe debugging tools (e.g., Abendaid, MaxUtil, SyncSort).</li>
<li>Ability to work both independently and as a collaborative team member within a structured SDLC environment.</li>
<li>Active or adjudicable Tier 3 / Noncritical-Sensitive (IT-II) background investigation.</li>
<li>Must be a U.S. citizen; males born after 12/31/1959 must be registered with Selective Service.</li>
</ul>
Preferred Qualifications
<ul>
<li>Prior DRAS program experience (RCPS, APS, and/or CRSC subsystems) strongly preferred.</li>
<li>Experience with DoD or federal payroll processing systems; familiarity with DoD FMR Vol. 5 financial management regulations a plus.</li>
<li>Proficiency with ADS-Online, ADS-Batch, MQ Series, CA Librarian, CA-View/DocView, Control-M, Connect Direct, or other third-party tools in the DRAS technology stack.</li>
<li>Familiarity with SQL and structured query design for production data research.</li>
<li>Exposure to Agile or iterative SDLC methodologies in legacy mainframe environments.</li>
<li>Experience with or understanding of PeopleSoft Global Payroll in a DoD context.</li>
</ul>
Work Environment & Security Requirements
<ul>
<li>Primary performance at DFAS Cleveland, Bratenahl, or Indianapolis; remote/telework permitted with COR approval, subject to security restrictions.</li>
<li>Must be available outside standard core hours (nights/weekends) when mission dictates, as coordinated by the Technical Lead and COR.</li>
<li>All work performed exclusively on Government-Furnished Equipment (GFE); personally-owned devices may not be used for government information or systems access.</li>
<li>Contractor personnel must report to DFAS-IN during the first week of contract performance for onboarding and CAC issuance.</li>
<li>Foreign travel requires DFAS Form 9133 submission not less than 30 days prior to departure</li>
</ul>

Journeyman Computer Programmers

Journeyman Computer Programmer

Five experienced Journeyman Computer Programmers for DRAS mainframe modernization; COBOL, JCL, CICS, SQL, IVR/ADS tools knowledge; SDLC experience and DoD/DFAS context.

CSS is seeking an experienced Technical Lead to serve as the senior technical authority within a six-person Journeyman Computer Programmer team supporting DRAS at DFAS. This individual will direct day-to-day technical execution, establish and enforce coding standards, conduct peer reviews, lead code turnovers, and serve as the primary technical liaison between the contractor development team and the DFAS DRAS Program Management Office (PMO). DRAS is an IBM z/OS mainframe-based system developed primarily in COBOL and CICS, processing $6 billion monthly in military retiree and annuity pay.
Key Responsibilities
Technical Leadership
<ul>
<li>Serve as the senior technical point of contact for the DRAS PMO and DRAS System Manager on all software development and maintenance matters.</li>
<li>Establish and enforce coding standards, unit testing protocols, and peer review procedures consistent with DRAS SDLC documentation and DFAS business processes.</li>
<li>Lead technical participation in System Requirements Reviews (SRRs), Critical Design Reviews (CDRs), Test Readiness Reviews (TRRs), and Post-Implementation Reviews (PIRs).</li>
<li>Provide technical mentorship and guidance to the five (5) Journeyman Computer Programmers; assign tasks, review work products, and ensure consistent quality.</li>
<li>Prepare and review system change specifications, design documents, and technical system documentation; identify and resolve discrepancies or inaccuracies.</li>
</ul>
Requirements Analysis & Software Development
<ul>
<li>Review and analyze System Change Requests (SCRs), point papers from R&A Operations, email requests, and meeting action items.</li>
<li>Lead preparation of written impact analyses for proposed changes, identifying all affected system components and producing Level of Effort (LOE) estimates accurate to +/- 15% of actuals.</li>
<li>Coordinate all impact analysis responses with the DRAS System Manager prior to submission.</li>
<li>Produce COBOL code and associated Job Control Language (JCL) for z/OS mainframe systems meeting SCR specifications and DRAS design document requirements, free of defects.</li>
<li>Develop in COBOL for z/OS 2.1, CICS, ADS-Online, ADS-Batch, MQ Series, and SQL; utilize VSAM, IDMS, and DB2 as required.</li>
<li>Ensure all developed software meets industry best practices, DRAS-defined business processes, and DFAS CMM Level 3 standards.</li>
</ul>
Testing & Code Turnover
<ul>
<li>Lead code walkthroughs to ensure all defects are identified prior to production turnover.</li>
<li>Coordinate and facilitate Peer Review meetings; present technical findings on defects, code efficiency, and conformance with coding standards.</li>
<li>Verify completion of all required testing plans and results prior to approving code turnover.</li>
<li>Ensure at least 95% of Customer Acceptance Testing (CAT) test cases pass without defects prior to production release.</li>
<li>Move approved code into designated staging areas and notify appropriate DFAS parties when code is production-ready.</li>
</ul>
Production Support & Issue Resolution
<ul>
<li>Provide direct production support to resolve payroll processing issues affecting RCPS, APS, and CRSC subsystems.</li>
<li>Lead root cause analysis and resolution for production anomalies; document 100% of reported situations in accordance with DFAS business processes.</li>
<li>Monitor production performance and production job execution; proactively identify and escalate emerging issues.</li>
<li>Participate in ad hoc user meetings as needed to support application issue resolution.</li>
</ul>
Agile & Process Compliance
<ul>
<li>Lead the team's participation in the DRAS Agile transformation effort; attend DFAS-sponsored Agile Boot Camp training and meet defined maturity expectations.</li>
<li>Execute data queries to support detailed requirements reviews and identify relevant data conditions.</li>
<li>Comply with DFAS-defined timeframes for program analysis, programming, unit testing, and pre-implementation support.</li>
<li>Maintain 95% monthly attendance at required team meetings; ensure team adherence to meeting participation requirements.</li>
</ul>
Required Qualifications
<ul>
<li>Bachelor's degree in Computer Science, Information Systems, or related technical field; or equivalent combination of education and directly applicable experience.</li>
<li>Minimum 8 years of hands-on IBM mainframe development experience, including at least 5 years in a technical lead or senior developer capacity.</li>
<li>Expert-level proficiency in COBOL for z/OS, CICS, and JCL; strong working knowledge of VSAM, DB2, and IDMS.</li>
<li>Experience with z/OS 2.1, TSO/ROSCOE, CA Librarian, CA-View/DocView, Control-M, and related mainframe tools.</li>
<li>Demonstrated experience conducting peer reviews, code walkthroughs, and leading structured software development teams.</li>
<li>Prior experience supporting DoD payroll or financial management systems preferred; DRAS/RCPS/APS experience highly preferred.</li>
<li>Active or adjudicable Tier 3 / Noncritical-Sensitive (IT-II) background investigation.</li>
<li>Must be a U.S. citizen; males born after 12/31/1959 must be registered with Selective Service.</li>
</ul>
Preferred Qualifications
<ul>
<li>Direct prior DRAS program experience (RCPS, APS, CRSC).</li>
<li>Familiarity with PeopleSoft Global Payroll v9.2 in the context of DFAS ERP modernization efforts.</li>
<li>Experience with MQ Series, SyncSort, Abendaid, MaxUtil, and other third-party tools in the DRAS stack.</li>
<li>Exposure to Agile SDLC in a mainframe environment; Scrum or SAFe certification a plus.</li>
<li>Experience with DFAS or DoD FMR Vol. 5 payroll financial management regulations.</li>
</ul>
Work Environment & Security Requirements
<ul>
<li>Primary performance at DFAS Cleveland, Bratenahl, or Indianapolis; remote/telework permitted with COR approval, subject to security restrictions.</li>
<li>Must be available outside standard core hours (nights/weekends) when mission needs dictate, as coordinated with the COR.</li>
<li>All work performed on Government-Furnished Equipment (GFE); use of personally-owned devices for government information is prohibited.</li>
<li>Foreign travel requires DFAS Form 9133 submission not less than 30 days prior to departure.</li>
</ul>

Technical Lead / Cobol Programmer

Technical Lead

Senior-level COBOL mainframe lead with 8+ years of IBM z/OS development, DoD payroll domain experience, and strong leadership.

About us One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration. The day-to-day <ul style="margin-top: 0in;"><li style="margin-bottom: 0in;">Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications</li><li style="margin-bottom: 0in;">Develop testbenches and help maintain and update system level verification environment</li><li style="margin-bottom: 0in;">Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs</li><li style="margin-bottom: 0in;">Develop timing constraints, analyze timing results, and implement design changes required to close timing</li><li style="margin-bottom: 0in;">Generate and collaborate on required design documents, development requirements, specifications and verification protocols</li><li style="margin-bottom: 0in;">Responsible for owning and driving technical issues to resolution</li><li style="margin-bottom: 0in;">Integrate and debugs design in the laboratory</li></ul> What you'll need <ul><li style="margin-bottom: 0in;">Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field</li><li style="margin-bottom: 0in;">5-8 years FPGA design experience, including Xilinx Vivado</li><li style="margin-bottom: 0in;">Strong knowledge of System Verilog</li><li style="margin-bottom: 0in;">Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders</li><li style="margin-bottom: 0in;">Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development</li><li style="margin-bottom: 0in;">Work independently, take initiative, and take ownership of tasks and results</li><li style="margin-bottom: 0in;">Strong written and verbal communication skills, ability to work with a geographically distributed team</li></ul>  What will help you on the job <ul><li>Familiarity with Matlab</li><li>Experience with GitHub</li><li>Experience with developing code for legacy Viasat modem platforms</li><li>Familiarity with DVB-S2x and DVB-RCS2 standards</li><li>Understanding and knowledge of Satellite communication waveforms and standards</li></ul>  Salary range $155,500.00 - $246,000.00 / annually.
For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat’s comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits. EEO Statement Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click <a href="mailto:careers@viasat.com" target="_blank" rel="noopener">here</a>.

Programmable Logic Design Engineer

Bachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.

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