Explore 8 python data engineer jobs from 4 hiring companies in Falls City, OR, US. Filter by remote, salary, experience, and company, then open any listing to apply.

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Python Data Engineer Jobs

Intel

Lam Research

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<div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>The group you’ll be a part of</b></H2></div><div><p style="text-align:justify"> </p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">The Office of the CTO is where innovation takes center stage. We inspire our global technical community to take on grand challenges, understand emerging trends, identify the critical inflections, and drive our sustainability, Environment, Social, and Governance (ESG) practices that will define the next generation of semiconductors and continued impact.</span></span></p>

<p> </p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>The impact you’ll make</b></H2></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">As a Virtual Process Engineer at Lam, you’ll be at the forefront of driving innovation and adoption of our internal process modelling software. You’ll support fast product evolution through agile processes, and utilize the capabilities of our computational products to support process engineering teams. You’ll help  solve Lam’s most difficult process engineering problems, train the engineering community in software usage, and interface with developers to identify new features, test releases, and ensure product quality. With your expertise and initiative, you’ll turn ideas into great products that support advancements in Lam’s semiconductor technology. </span></p>
<p><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">In this role, you will have a significant impact on the innovation and efficiency of Lam's products and services. Utilizing our innovative software products, you will enable data-driven decision making, optimize workflows, enhance user experience, and improve quality and performance of Lam's hardware and processes.</span> </p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>What you’ll do</b></H2></div><div><ul>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Responsible for driving adoption of internal software products across etch and deposition product groups. </span></li>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Work with application team and process engineers in the planning, data collection, modeling, data analysis, and reporting of results to process teams and other stakeholders. </span></li>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Work with process engineers and other teams cross functionally to understand roadmaps, process flow, inflection points, requirements, and business issues/ challenges. </span></li>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Work with product managers and developers to ensure required capabilities are available for applications and provide requirements and user stories. </span></li>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Contributes to product development, release activities, and software training. </span></li>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Acts as single point of contact accountable for applications. </span></li>
<li><span style="font-size:14.0pt;font-family:arial, helvetica, sans-serif">Brings innovation to design and architecture, working closely with product teams, and owning specific aspects of feature developmen</span>t. </li>
</ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Who we’re looking for</b></H2></div><div><ul>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Bachelor’s degree in physics, chemistry, chemical engineering, materials science, or related field with 10+ years of experience; or Master’s degree with 8+ years’ experience; or a PhD with 5+ years’ experience; or equivalent experience.  </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Experience scripting in Python and utilizing python packages for data analysis and visualization </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Strong background in physics, chemistry, materials science, or other relevant fields of study </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Experience with working with multi-variant problems through advanced data analysis methods. </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Basic knowledge of semiconductor unit process development and integration schemes  </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Strong organizational skills and demonstrated ability to manage multiple tasks simultaneously and ability to react to shifting priorities to meet business needs and deadlines. </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Excellent people skills with demonstrated ability to work effectively and efficiently with diverse teams, customers, internal and external partners. </span></li>
</ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Preferred qualifications</b></H2></div><div><ul>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Experience with high performance computing, machine learning, and scripting using Python or other relevant scripting languages. </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Expertise in plasma physics and plasma-based etch/deposition chamber fundamentals. </span></li>
<li><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">In-depth understanding of semiconductor process development for deposition and etch products and working knowledge of process modeling. </span></li>
</ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Our commitment</b></H2></div><div><p style="text-align:justify"> </p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results.</span></span></p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Company's intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees.</span></span></p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif"><em>Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories – On-site Flex and Virtual Flex. ‘On-site Flex’ you’ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. ‘Virtual Flex’ you’ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.</em></span></span></p></div></div></div><p><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif"><b>Our Perks and Benefits</b></span></span></p>

<p><br>
<br>
<span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">At Lam, our people make amazing things possible. That’s why we invest in you throughout the phases of your life with a comprehensive set of outstanding benefits. </span></span></p>

Senior Virtual Process Engineer (Tualatin, OR, US, 97062)

Process Engineer

Bachelor’s in physics, chemistry, chemical engineering, materials science, or related field with 10+ years of experience; or Master’s with 8+ years; or PhD with 5+ years; plus Python data analysis and strong collaboration skills.

Home | Lam Research

<div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>The group you’ll be a part of</b></H2></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">In the Global Products Group, we are dedicated to excellence in the design and engineering of Lam’s etch and deposition products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry.  </span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>The impact you’ll make</b></H2></div><div><p><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">Lam Research is looking for a Performance Data Scientist in Lam’s Global Quality organization. This is individual will partner with the Field/Factory Business Process Quality Manager, Global Quality peers and leaders across the company to identify through the use a common data to effectively prioritize and resolve the largest quality issues in the company impacting our customers and limiting our ability to meet both short and term business objectives. This role will have a high-profile presence within the organization and will be able to contribute and make a difference in the quality performance and culture through knowledge, leadership and influence within the company and ultimately delivering required improvement to our valued customers and internal functions. </span></p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>What you’ll do</b></H2></div><div><ul>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Improve quality performance consistently from awareness, prioritization and action through the availability of common data.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Analyze trends and patterns in quality data that drive required quality improvement.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Develop tools, metric measurement and assessment methods for performance management and predictive modeling.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Foster growth and utility of Cost of Quality within the company through correlation of I&amp;W data, ECOGS, identification of causal relationships for quality events and discovery of hidden costs throughout the network.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Reliability tracking and improvement and problem resolution.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Improve data utilization via AI, automation and improve defect determination leading to real time resolution and speeding systemic action.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Create accountability for corporate-wide quality data analysis and action.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Lead and/or advise on multiple projects simultaneously and demonstrate organizational, prioritization, and time management proficiencies.</span></li>
</ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Who we’re looking for</b></H2></div><div><div><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt"> 5–7+ years of continuous improvement experience, including analytical work, project management, and business analysis.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Bachelor’s degree in engineering, quality, computer science, or related field; Master’s preferred.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Semiconductor industry experience.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Strong expertise in advanced statistics, multivariate modeling, machine learning, and modeling of physical/electro‑mechanical systems.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Demonstrated success implementing AI solutions that drive efficiency and effectiveness across the organization.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Ability to define problem statements, set objectives, design analytical approaches, and execute analyses/experiments.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Proven leadership overseeing large, complex programs from discovery through implementation and support for internal and external stakeholders.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Skilled at influencing within a fast‑paced, cross‑functional, matrixed environment.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Excellent communication, collaboration, interpersonal, and influencing skills.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Proficiency in Python, R, MATLAB, or similar programming environments.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Knowledge of Lean Six Sigma, statistics, and quality systems.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Ability to manage multiple projects simultaneously.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Experience with Quickbase and Power BI development.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Strong executive‑level presentation skills.</span><br><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">• Outstanding people skills and effectiveness in matrix organizations.</span></div></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Preferred qualifications</b></H2></div><div><ul>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Demonstrated success in using structured problem-solving methodologies and quality tools to solve complex problems.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Command over quality tools such as Pareto FMEA /Fault tree diagram/Fish bone diagram etc.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Willingness to adapt best practices via benchmarking.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Knowledge of programming environments such as Python, R, Matlab, or equivalent.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Six Sigma certification (Green Belt or higher).</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Advanced expertise in structured problem-solving methodologies (PDCA, DMAIC, 8D) and quality tools.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Experience in semiconductor capital equipment industry.</span></li>
<li style="list-style-type:none;font-family:arial, helvetica, sans-serif;font-size:14.0pt"><span style="font-family:arial, helvetica, sans-serif;font-size:14.0pt">-Experience in Statistical Process Control (SPC), Gage R&amp;R, Pareto Charts etc. using tools like JMP, Minitab.</span></li>
</ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Our commitment</b></H2></div><div><p style="text-align:justify"> </p>
<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results.</span></span></p>
<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Company's intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees.</span></span></p>
<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif"><em>Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories – On-site Flex and Virtual Flex. ‘On-site Flex’ you’ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. ‘Virtual Flex’ you’ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.</em></span></span></p>
<p style="text-align:justify"><span style="font-size:16.0px;color:white"><span style="font-family:Arial, Helvetica, sans-serif"><em>#LI-RSC1 </em></span></span></p></div></div></div><p><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif"><b>Our Perks and Benefits</b></span></span></p>

<p><br>
<br>
<span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">At Lam, our people make amazing things possible. That’s why we invest in you throughout the phases of your life with a comprehensive set of outstanding benefits. </span></span></p>

Data Scientist 4 (Tualatin, OR, US, 97062)

Data Scientist

5–7+ years experience in analytics/continuous improvement; bachelor’s in engineering/quality/computer science; semiconductor industry experience; strong statistics, ML, Python/R; leadership and cross-functional collaboration; proficiency in Python, R, MATLAB; experience with Quickbase and Power BI.

<div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>The group you’ll be a part of</b></H2></div><div><p style="text-align:justify"> </p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">In the Global Products Group, we are dedicated to excellence in the design and engineering of Lam’s etch and deposition products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry. </span></span></p>

<p> </p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>The impact you’ll make</b></H2></div><div><div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">We are seeking a top-tier candidate to work on integration, testing, and analysis of diverse sensor technologies—including vision systems and other time-series sensors—for our advanced products. The ideal candidate will work in a cross-functional role, collaborating with engineering teams and vendors to develop robust infrastructure for accurate data acquisition, processing, and performance validation. This role also involves supporting field teams virtually or on-site as needed.</span></div></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>What you’ll do</b></H2></div><div><ul>
<li style="font-size:12.0pt"><span style="font-family:Arial, Helvetica, sans-serif;font-size:12.0pt">Collaborate with cross-functional and cross-cultural teams to guide the specification and development of products.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Debug optical, electrical, mechanical, and signal integrity issues during sensor module development.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Perform comprehensive characterization of imaging sensors, time-series sensors (e.g., thermal, acoustic, vibration), and associated signal processing pipelines.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Collaborate with cross-functional teams to identify, implement, and validate improvements in sensor data capture and processing across hardware and software.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Apply engineering theories and research techniques to investigate, troubleshoot, and resolve technical challenges.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Plan and execute research to advance sensor analytics, including image/video processing and time-series signal analysis for semiconductor equipment.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Develop algorithms and workflows for sensor fusion, anomaly detection, and predictive modeling using multi-modal data.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Assess effectiveness and accuracy of models and data acquisition techniques.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Develop, train, and deploy models for optimizing customer experience and equipment reliability.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Create test plans, documentation, and reports for sensor validation and performance metrics.</span></li>
<li style="font-size:12.0pt"><span style="font-size:12.0pt">Support process engineers by running recipes and coordinating sensor-based measurements on process modules..</span></li>
<li style="font-size:12.0pt"><span style="font-family:Arial, Helvetica, sans-serif;font-size:12.0pt">Maintain a high degree of customer engagement including face-to-face and international travel to customer sites supporting near term product releases and solve customer issues.</span></li>
<li style="font-size:12.0pt"><span style="font-family:Arial, Helvetica, sans-serif;font-size:12.0pt">Work in a cleanroom lab and/or customer semiconductor fab environment.</span></li>
</ul>
<p> </p>
<p> </p></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Who we’re looking for</b></H2></div><div><p><span style="font-family:Arial, Helvetica, sans-serif;font-size:12.0pt"><strong>Minimum Qualifications:</strong></span></p>
<ul>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">BS/MS/PhD in Electrical Engineering, Computer Science, Mechanical Engineering, Physics, Applied Mathematics, or related disciplines.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Strong experience in signal processing, sensor integration, and data analysis for imaging and non-imaging sensors.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Proficiency in image processing, computer vision, and time-series analysis algorithms.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Expertise in scripting languages such as Python or MATLAB; familiarity with scientific computing libraries.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Knowledge of sensor calibration methods (e.g., camera calibration, sensor alignment) and data acquisition systems.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Familiarity with software test methodologies, Design of Experiments, and performance validation.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Strong problem-solving and troubleshooting skills across hardware and software domains.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Ability to learn new technologies and complete projects with minimal guidance.</span></div>
</li>
<li style="font-size:12.0pt">
<div><span style="font-size:12.0pt">Comfortable with multiple software tools and basic system/network troubleshooting.</span></div>
</li>
</ul></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Preferred qualifications</b></H2></div><div><ul>
<li>
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">Experience with Python and the scientific stack (NumPy, SciPy, Pandas, OpenCV).</span></div>
</li>
<li style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">Background in sensor fusion, anomaly detection, and predictive analytics.</span></div>
</li>
<li style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">Working knowledge of network protocols and streaming data analytics.</span></div>
</li>
<li style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">Experience with thermal imaging, spectroscopy, vibration/acoustic sensors, or other non-vision sensing modalities.</span></div>
</li>
<li style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">Familiarity with semiconductor processing and equipment operations (Lam Research experience is a plus).</span></div>
</li>
<li style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">Exposure to machine learning techniques for image classification, segmentation, and time-series forecasting.</span></div>
</li>
</ul>
<div><span style="font-family:arial, helvetica, sans-serif;font-size:12.0pt">In this role, you will partner with subject matter experts and collaborate with hardware, electrical, software, and algorithm teams to build representative test systems and prototypes for multi-sensor integration and analytics.</span></div></div></div><div style="padding:10.0px 0.0px;border:1.0px solid transparent"><div style="font-size:16.0px;word-wrap:break-word"><H2 style="font-size:1.0em;margin:0.0px"><b>Our commitment</b></H2></div><div><p style="text-align:justify"> </p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results.</span></span></p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Company's intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees.</span></span></p>

<p style="text-align:justify"><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif"><em>Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories – On-site Flex and Virtual Flex. ‘On-site Flex’ you’ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. ‘Virtual Flex’ you’ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time.</em></span></span></p></div></div></div><p><span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif"><b>Our Perks and Benefits</b></span></span></p>

<p><br>
<br>
<span style="font-size:16.0px"><span style="font-family:Arial, Helvetica, sans-serif">At Lam, our people make amazing things possible. That’s why we invest in you throughout the phases of your life with a comprehensive set of outstanding benefits. </span></span></p>

Product Engineer 3 (Tualatin, OR, US, 97062)

Product Engineer

BS/MS/PhD in engineering or related fields; strong signal processing, sensor integration, data analysis; Python/MATLAB; sensor calibration and validation; cross-functional collaboration.

<p style="text-align: center;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><strong><span style="color: black;">SYSTEMS TEST ENGINEER</span></strong></span></p>
<p><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;"><strong><u><span style="color: black;">PRIMARY FUNCTION</span></u></strong></span></p>
<p style="text-align: justify;"><span style="font-size: 8pt; font-family: verdana, geneva, sans-serif; color: black;">As a member of the Engineering Department, the Systems Test Engineer plays a pivotal role is shaping the performance, safety, and craftsmanship of SawStop products. The Systems Test Engineer will lead system-level requirements definition and validation efforts across complex mechanical, electromechanical, and software platforms. They will also lead the development of test plans and test platforms that assess the quality, reliability, and function of products, components, and systems at an appropriate level of confidence to represent the SawStop brand. This role will operate on either side of the first few levels of the Systems V-Model.</span></p>
<p style="text-align: justify;"><span style="font-size: 8pt; font-family: verdana, geneva, sans-serif; color: black;">The Systems Test Engineer will be a key contributor to developing appropriate technical product specifications, verification test procedures, sampling sizing, and serve as a statistics technical resource within the department. As a member of the Engineering Department, you will prioritize safety of yourself and team members while maintaining high quality standards and driving efficiency gains within your test plans. The position involves proactive, professional communication and a high degree of collaboration and coordination across cross functional groups and reporting structures. Regular supervision is not required, although regular reporting to multiple stakeholders and proactive communication is essential for this role.</span></p>
<p><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;"><strong><u>DUTIES &amp; RESPONSIBILITIES</u></strong></span></p>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">System-Level Testing</span>
<ul>
<li style="text-align: justify;"><span style="font-size: 8pt; font-family: verdana, geneva, sans-serif;">Develop system-level requirements and execute system‑level test plans, procedures, and protocols that validate product meets customer needs within project constraints.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Establish test methodologies that reflect real‑world woodworking scenarios.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Perform functional, performance, environmental, reliability, and compliance testing.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Validate system interactions across mechanical, electrical, firmware, and software components.</span></li>
</ul>
</li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Test Planning &amp; Documentation</span>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Contribute to translating product requirements and specifications into measurable test criteria.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Create detailed test documentation, including test cases, test reports, and maintain traceability to product requirements.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Maintain test records to support regulatory, safety, and quality audits.</span></li>
</ul>
</li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Hands-On Testing &amp; Analysis</span>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Develop custom test platforms utilizing data acquisition systems and knowledge if sensors and instrumentation.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Operate test equipment such as oscilloscopes, environmental chambers, thermal cameras, load cells, sound meters, and other instrumentation.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Collect, analyze, and interpret test data to identify trends, anomalies, and root causes.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Troubleshoot system failures and collaborate with engineering teams to drive corrective actions.</span></li>
</ul>
</li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Cross-Functional Collaboration</span>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Collaborating with cross-functional teams to ensure system testing strategies align with business goals and customer needs.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Providing feedback and recommendations to improve product design, functionality, and usability based on test outcomes.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Participate in design reviews, risk assessments (FMEA), and verification planning.</span></li>
</ul>
</li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Process &amp; Quality Improvement</span>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Develop new test setups, fixtures, and automation tools that enhance repeatability, throughput, and insight.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Improve test methodologies, workflows, and tools to increase efficiency and coverage.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Support continuous improvement initiatives in product development and testing processes.</span></li>
</ul>
</li>
</ul>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;"><strong><u>REQUIRED QUALIFICATIONS</u></strong></span></p>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Bachelor of Science degree in Mechanical, Electrical, Systems, or related engineering field.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">3+ years' experience in systems or test engineering or defining and executing tests in another engineering role.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Experience with designing and performing system level testing of physical or electromechanical products; ideally in power tools, machinery, or industrial equipment.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Able to operate on both sides of the System V-Model.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Broad proficiency with engineering fundamentals (mechanical, electrical, software, or systems).</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Familiarity with electrical systems, motor controllers, and safety circuits.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Broad hands-on expertise using lab equipment, sensors, and instrumentation to perform mechanical and electrical tests.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Experience with designing and implementing data acquisition and automated test systems.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Practical working understanding of engineering specifications, mechanical drawings, electrical schematics.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Green belt in DFLSS or equivalent practical applied statistical knowledge, especially MSA, Gauge R&amp;R, and DOE.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Proven ability to lead complex test programs and influence cross‑functional engineering teams.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Strong analytical and problem-solving skills.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Excellent communication and documentation abilities.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">High proficiency using Microsoft Office tools (PowerPoint, Excel, Word, Outlook).</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Must work locally in Tualatin office.</span></li>
</ul>
<p style="text-align: justify; page-break-after: avoid; tab-stops: 171.55pt;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;"><strong><u>PREFERRED QUALIFICATIONS</u></strong></span></p>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Master of Science degree in Mechanical, Electrical, Systems, or related engineering field.</span></li>
<li style="text-align: justify;"><span style="color: black; font-family: verdana, geneva, sans-serif; font-size: 8pt;">5+ years of experience in a systems or test engineering role.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Experience with woodworking machinery, or other rotating/cutting equipment, and knowledge of woodworking processes and materials.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Experience with environmental or reliability testing (thermal, vibration, shock, ingress protection).</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Experience with reliability engineering, accelerated life/stress testing, and statistical modeling</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Experience with test automation (Python, LabVIEW, MATLAB, etc.).</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Knowledge of embedded systems, firmware behavior, or control systems.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Familiarity with firmware validation methods.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Black belt in DFLSS or equivalent practical applied statistical knowledge.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Working knowledge of applicable product standards, for example UL, ANSI, ISO, IEC etc.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Background in manufacturing test or design verification testing.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Working knowledge of SolidWorks 3D CAD and SolidWorks PDM.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Working knowledge of source code control for software development.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Familiarity with using Jira and Confluence.</span></li>
</ul>
<p style="tab-stops: .25in;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;"><strong><u>COMPANY OVERVIEW</u></strong></span></p>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">SawStop is the world leader in power tool safety.</span></p>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Headquartered in Tualatin, Oregon, SawStop is the #1 manufacturer of table saws for both commercial and hobbyist markets. Our safety technology has saved thousands of users from devastating, life-changing table saw injuries. As part of the TTS Group, a 2,500+ employee family-owned company based in Germany, we are focused on long-term growth.</span></p>
<p style="text-align: justify;"><span style="color: black; font-family: verdana, geneva, sans-serif; font-size: 8pt;">We design, engineer, and manufacture innovative woodworking power tools and accessories for amateur and professional markets. All SawStop power tools feature our patented safety technology that has saved tens of thousands of users from devastating, life-changing table saw injuries.</span></p>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Our commitment to quality, innovation, and safety over the past 20 years has made us the industry leader. We're a passionate, collaborative, and intellectually curious group of over 100 professionals who care as much about each other as we do our product. Focused on innovation and best-in-class quality, we are always looking for smart creative thinkers to expand our product line and reach new markets</span></p>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;"><strong><u>BENEFITS</u></strong></span></p>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Our Team Members are what make SawStop special. That's why we're committed to taking care of our team through a comprehensive benefits program.</span></p>
<ul>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Employee-Centered Medical Plan &ndash; 95% paid for the employee and eligible dependents.</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Available Health Savings Plan</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Available Flexible Saving Account - Health Care/Dependent Care</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">100% Paid Dental</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">100% Paid Vision</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Basic Life and AD&amp;D Insurance</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Short Term and Long-Term Disability Insurance</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Mental Health and Wellness Resource</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Employee Assistance Program</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">401k Retirement Plans with Company Match</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Paid Time Off and Holidays</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Tutoring Support for Team Member's Kids (Grades K-12)</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Competitive Compensation Package</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Opportunities for Professional Development</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Job-Related Education Assistance Program</span></li>
<li style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 8pt;">Hybrid Work Schedule</span></li>
</ul>
<p style="text-align: justify;">&nbsp;</p>
<p style="text-align: justify;"><span style="font-family: verdana, geneva, sans-serif; font-size: 10pt;"><strong><em>Please include cover letter and current resume when applying.</em></strong></span></p>

Systems Test Engineer

3+ years in systems or test engineering; experience with system-level testing of electromechanical products; proficiency with data acquisition, test equipment, and statistics.

<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description:&nbsp;</h2><p>Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you&#39;ll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.</p><p><a href="https://jobs.intel.com/en/life-at-intel" target="_blank">Life at Intel</a></p><p></p><p>About the team and organization: Compact Device Modeling Group (CDMG) is part of Intel&#39;s Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies. As a member of CDMG you will be at the forefront of co-optimizing Intel&#39;s state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications.<br />As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel&#39;s new technologies.</p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.</p><p><br /><b>Minimum Qualifications</b><br />• Bachelor&#39;s degree in Electrical Engineering or a related discipline and 5&#43; or</p><p>Master&#39;s degree in Electrical Engineering or a related discipline and at least 3 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline.</p><p>• Graduate coursework or research experience in semiconductor device physics or 5&#43; years of work experience in Semiconductor device physics.<br />• 1&#43; years&#39; experience Python scripting for data analysis, automation and documentation.</p><p></p><p><br /><b>Preferred Qualifications</b><br />• Ph.D. in Electrical Engineering or a related discipline with 3&#43; years of industry experience in the semiconductor field.<br />• Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.<br />• Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA) including experience in one or more of the following areas:</p><ul><li>Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance.</li><li>Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.</li><li>Modeling using Open Model Interface (OMI).</li><li>Strong understanding of process flow, layout, and basic circuit design/simulation.</li><li>Modeling self-heating effects and their influence on device and circuit performance.</li><li>Proven capability to collaborate across multiple teams and geographies.</li><li>Experience with machine learning algorithms and their application is data analysis and compact model development.</li></ul><p></p><p></p><p><b><span>Benefits at Intel</span></b></p><p><span>Our total rewards package goes above and beyond just a paycheck. Whether you&#39;re looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to </span><span><a href="https://jobs.intel.com/en/benefits" target="_blank"><b><span>Intel Benefits | Intel Careers</span></b></a></span><span> for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. </span></p><p></p><p style="text-align:inherit"></p><p style="text-align:inherit">          </p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Type:</h2>Experienced Hire<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (United States of America)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location:&nbsp;</h2>US, Oregon, Hillsboro<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2>US, California, Santa Clara<p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.  We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p></p><h2>Benefits</h2><p></p><p>We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the <a target="_blank" href="https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003"><span style="color:#0000ff"><u>benefits of working at Intel</u></span></a>. </p><p> </p><p> </p>Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD<p> </p><p> </p>The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.<p> </p><p> </p><p style="text-align:inherit"></p><p style="text-align:left"><b>Work Model for this Role</b></p>This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Semiconductor Device Modeling Engineer

Bachelor's/Master's/PhD in EE with 3+ years; Python data analysis; BSIM-CMG/compact models; HSPICE/Spectre; ML exposure.

<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description:&nbsp;</h2><p><b>About Intel Foundry</b></p><p>At Intel Foundry, our Technology Development and Manufacturing teams power a worldwide network of cutting edge fabs and assembly/test facilities. To keep pace with an aggressive technology roadmap, we are pushing the limits of transistor and interconnect reliability delivering faster time to data and higher quality insights that directly shape Intel&#39;s and our foundry customers&#39; most advanced process technologies.</p><p></p><p><b>The Opportunity</b></p><p>Join the Stress Testing and Reliability (STaR) Lab as part of the Foundry Lab Network (FLN), within the broader Foundry Quality, Reliability, and Labs (FQRL) organization. You&#39;ll help develop and enable efficient, high-quality reliability testing, with hands-on exposure to reliability characterization of transistors, interconnects, and other devices on today&#39;s and tomorrow&#39;s technology nodes.</p><p><b>Location:</b> Intel&#39;s Ronler Acres campus in Hillsboro, Oregon—just outside Portland in the beautiful Pacific Northwest, offering an outstanding quality of life alongside world-class engineering challenges.</p><p></p><p><b>What You&#39;ll Do</b></p><p>As a Quality and Reliability R&amp;D Lab Engineer in Intel&#39;s Reliability Labs, you will be at the center of enabling the reliability data collection that underpins our most advanced process technologies. In this role, you will own, develop, and manage a suite of lab tools ensuring they are fully maintained, production ready, and capable of delivering high quality, data.</p><p></p><p><b>Core Responsibilities:</b></p><ul><li><b>Technical Problem Solving:</b> Drive root cause investigations when issues arise</li><li><b>Continuous Improvement:</b> Lead improvement projects that enhance data integrity, tool performance, automation, and overall lab efficiency</li><li><b>Capability Development:</b> Design, develop, and qualify new tools, test methodologies, and workflows for characterizing device reliability</li><li><b>Cross-functional Collaboration:</b> Work closely with lab operations, industrial engineers, module engineers, and external vendors</li><li><b>Documentation &amp; Transfer:</b> Ensure new processes and methods are robustly developed, documented, and smoothly transferred to operations</li></ul><p></p><p><b>Development Focus Areas:</b></p><ul><li>Design and qualify new reliability stress techniques for transistors,  and interconnects</li><li>Build next-generation reliability stress infrastructure including hardware, software, procedures, and documentation</li><li>Support pathfinding, technology development, and certification milestones for Intel and foundry customers</li><li>Model world-class safety, quality, and operational excellence</li></ul><p></p><p><b>The successful candidate must demonstrate the following:</b></p><ul><li>Proven verbal and written communication skills</li><li>Team player with proven skills to collaborate and influence in heterogenous team</li><li>Proven skills to perform successfully in a fast paced, high pressure team environment</li></ul><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.</p><p></p><p><b>Note: </b></p><p></p><p><b>For information on Intel’s immigration sponsorship guidelines, please see </b></p><p><a href="https://www.intel.com/content/www/us/en/jobs/hiring.html" target="_blank"><b>Intel U.S. Immigration Sponsorship Information</b></a></p><p></p><p><b>Minimum Qualifications and Experience</b>:</p><p></p><p>A minimum of a Master&#39;s degree in Electrical Engineering/Physics/related field with 3&#43; years of experience on electrical characterization of electronic materials and devices.</p><p></p><p>In addition, you must have 3&#43; years of experience in the following:</p><ul><li>Experience in semiconductor electrical characterization, device testing, and troubleshooting using parametric analyzers, oscilloscopes, and related equipment</li><li>Leadership experience in technical organizations</li><li>Project management skills</li><li>Statistics with practical experience using JMP</li><li>Experience applying statistical analysis techniques to experimental data; proficiency with JMP or equivalent</li><li>Experience with hardware automation, preferably using LabVIEW, TestStand, or Python</li></ul><p></p><p><b>Preferred Qualifications and Experience</b>:</p><ul><li>PhD in Electrical Engineering, Physics, or a related field</li><li>Previous related work experience in a semiconductor foundry preferred</li><li>Experience of work and external vendors will be an advantage</li><li><p>Experience leading technical teams, influencing stakeholders, and managing resources and timelines in a matrixed environment</p></li><li>Familiarity with semiconductor device fabrication processes and packaging process flows</li><li>Delivering results in time-critical technical projects involving innovation and strategic planning</li><li>Problem-solving techniques and fundamental engineering concepts to create novel, efficient solutions</li></ul><p></p><p><br /><b>Why Join Us?</b></p><p>This is a highly visible, technically challenging role where your work will directly influence the reliability, performance, and time-to-market of current and future Intel process technologies. You&#39;ll be part of a dedicated team advancing the reliability stress capabilities needed to qualify both Intel&#39;s internal products and external foundry customers&#39; technologies.</p><p style="text-align:inherit"></p><p style="text-align:inherit">          </p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Type:</h2>Experienced Hire<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (United States of America)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location:&nbsp;</h2>US, Oregon, Hillsboro<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.  We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p></p><h2>Benefits</h2><p></p><p>We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the <a target="_blank" href="https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003"><span style="color:#0000ff"><u>benefits of working at Intel</u></span></a>. </p><p> </p><p> </p>Annual Salary Range for jobs which could be performed in the US: $133,800.00-188,890.00 USD<p> </p><p> </p>The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.<p> </p><p> </p><p style="text-align:inherit"></p><p style="text-align:left"><b>Work Model for this Role</b></p>This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Quality and Reliability R&D Lab Engineer

Master's degree in Electrical Engineering/Physics with 3+ years electrical characterization; project leadership; experience with JMP, LabVIEW/TestStand/Python; semiconductor testing and data analysis.

<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description:&nbsp;</h2><p>Advanced Packaging Technology and Manufacturing (APTM) is looking for a Platform Yield Analyst to join a team tasked with the objective of driving yield improvement across APTM&#39;s portfolio of advanced packaging technologies. As a Yield Platform Analyst, the successful candidate will set priorities for the team, get results across boundaries, ensure an inclusive work environment, and demonstrate progress to key yield milestones in support of platform certification timelines.</p><p></p><p>Responsibilities included but not limited to the followings:</p><ul><li>Define goals and roadmap for yield improvement for new packaging process technology and architectures throughout the development cycle. Independently drives recommendations and influences the Yield improvement roadmap with the necessary process flow, systems and methodology required to meet goals.</li><li>Establish relationships between critical material, tool and process modulators on yield and correlations to inline parameters.</li><li>Provides process development direction throughout the whole lifecycle of a technology from as early as pathfinding through ramp.</li><li>Performs statistical analysis, develops visualizations and presentations to construct accurate process development roadmaps that drive technology yield milestones.</li><li>Extracts insights from structured and unstructured data by quickly synthesizing large volumes of data, and applying statistics, machine learning and coding techniques.</li><li>Develops systems to transform complex experimental and manufacturing data into yield improvement actions using knowledge of product design and test features.</li><li>Ensures manufacturability over process and product design through thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp.</li><li>Monitor and evaluate completion of tasks and projects and lead task forces on integrated problems.</li><li>Work with both upstream, downstream and cross functional key partners to ensure successful pathfinding, development, and ramp of new technology into HVM. Some domestic and international travel may be needed. T</li></ul><p></p><p>The candidate should also exhibit the following behavioral traits or/and skills:</p><ul><li>Be capable of directing cross-functional teams and working effectively across organizational boundaries.</li><li>Tolerance of ambiguity and flexibility with respect to job roles and working hours.</li><li>Communication and presentation skills, especially to executives.</li><li>Analytical and problem-solving skills.</li></ul><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p><b>Qualifications</b></p><p></p><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.</p><p><b>Minimum Qualifications</b></p><p></p><p>Must possess a bachelor’s degree with 4&#43; years of relevant experience, OR Master&#39;s Degree with 3&#43; years of relevant experience, OR PhD Degree in Materials Science and Engineering or Mechanical Engineering or Computer Science or Information Systems or Chemical Engineering or Electrical Engineering or Chemistry or Physics or any other related discipline.</p><p></p><p>Experience listed above should be  a combination in the following:</p><ul><li>Applying materials, tools and process fundamentals and design process interactions to drive yield improvement projects.</li><li>Applying advanced data systems, tools and techniques for yield improvement.</li><li>Develop and deploy software related to Yield reporting and automated commonality analysis.</li></ul><p></p><p><b>Preferred Qualifications:</b></p><ul><li>Prior experience and ability to manage, mentor and coach technical engineers.</li><li>Detailed knowledge of substrate and/or assembly and/or fab back end processes.</li><li>Sense of ownership and experience working with partners to drive yield improvement.</li><li>Prior experience in integration, yield, or module engineering roles.</li><li>Data systems and analytics, Python, machine learning techniques, yield improvement methodologies.</li><li>Experience with JMP, JSL, SQL, Python programming.</li></ul><p style="text-align:inherit"></p><p style="text-align:inherit">          </p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Type:</h2>Experienced Hire<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (United States of America)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location:&nbsp;</h2>US, Oregon, Hillsboro<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2>US, Arizona, Phoenix<p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.  We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p></p><h2>Benefits</h2><p></p><p>We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the <a target="_blank" href="https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003"><span style="color:#0000ff"><u>benefits of working at Intel</u></span></a>. </p><p> </p><p> </p>Annual Salary Range for jobs which could be performed in the US: $133,800.00-188,890.00 USD<p> </p><p> </p>The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.<p> </p><p> </p><p style="text-align:inherit"></p><p style="text-align:left"><b>Work Model for this Role</b></p>This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION:  Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Yield Platform Analyst

Bachelor’s or higher in a related field with 4+ years, or Master’s with 3+ years, or PhD; experience in yield, data analysis, and programming; ability to lead cross-functional teams.

<p>Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You will be part of the team responsible for crafting state-of-the-art ASICs that are integral to many Apple products. We are looking for an engineer who will work on the modeling of power dissipation of various IPs and applications, including AI/ML and power modeling at the SOC/system level for Apple products. This role provides an opportunity to participate in optimization of a variety of leading edge chips for power-efficiency. You will collaborate across many teams including architecture, SOC design, and system design. The job also involves partnering with the lab and silicon characterization/validation teams on correlating the models to the silicon data.</p><h3>Description</h3><p>The job involves collaborating across many fields and playing a role of getting innovative products to millions of customers. You will have the opportunity to build new insights into silicon optimization, as well as work with architects, silicon design engineers, software developers, and be involved in silicon/model correlation efforts of mobile SoC design.</p><p>Your main responsibilities will be:</p><p>-Modeling power dissipation at the SOC level, including Neural Engines, CPUs, Graphics, compute ( AI/ML) accelerators, media IPs, caches and fabric.<br />-Modeling power dissipation for customer use-cases.<br />-Interacting with the System designers, Technology team, Silicon Validation, and Product Engineering teams to define power targets at the SOC level, and the power delivery.<br />-Working with the power lab and test teams to correlate models to silicon data.</p><h3>Minimum Qualifications</h3><ul><li>A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.</li></ul><h3>Preferred Qualifications</h3><ul><li>We would prefer our SoC Power Spec Engineer to have the following qualifications:</li><li>MSEE preferred</li><li>Deep knowledge of SOC architecture and power modeling.</li><li>Deep understanding of SOC building blocks including CPU, GPU, caches, memory and media IPs</li><li>Skills in scripting and data analysis.</li><li>Understanding of VLSI design flow and CMOS technology and background in EE.</li><li>Ability to understand and model thermal control loops and throttling mechanisms.</li><li>Strong teammate with excellent communication skills.</li></ul>

SoC Power Spec Engineer

Bachelor's degree in a relevant field and 3+ years of industry experience; strong power modeling and scripting skills; knowledge of SOC architecture and CMOS technology.

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