Career Opportunities: Sr. Silicon Design Engineer (181363)
What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
Senior DFT Engineer – Central DFX
The Role:
Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
The Person:
As a DFT Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
PRIMARY RESPONSIBILITY:
- Develop scan compression insertion and stitching flow automation
- Perform scan ATPG/DRC verification, pattern generation and simulation
- Collaborating with designers on STA, physical, power related issues
- Work with multi-functional teams and handling schedules
- The successful candidate may also be responsible of:
- Debugging and verifying block-/chip-level DFT/DFX features
- Porting or creating the DFT/DFX verification environment
- Block/chip test plan creation and development
- Stimulus writing and debug, and regression clean-up
KNOWLEDGE/SKILLS/ABILITY:
- DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus
- Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
- Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
- Familiar with Verilog design language, Verilog simulator and waveform debugging tools
- Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus
- Strong problem solving skills
- Team player with strong communication skills
EDUCATION:
Minimum B.Sc in Electrical or Computer Engineering (or equivalent)
Requisition Number: 181363
Job Function: Design
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
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What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
Senior DFT Engineer – Central DFX
The Role:
Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
The Person:
As a DFT Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
PRIMARY RESPONSIBILITY:
- Develop scan compression insertion and stitching flow automation
- Perform scan ATPG/DRC verification, pattern generation and simulation
- Collaborating with designers on STA, physical, power related issues
- Work with multi-functional teams and handling schedules
- The successful candidate may also be responsible of:
- Debugging and verifying block-/chip-level DFT/DFX features
- Porting or creating the DFT/DFX verification environment
- Block/chip test plan creation and development
- Stimulus writing and debug, and regression clean-up
KNOWLEDGE/SKILLS/ABILITY:
- DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus
- Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
- Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
- Familiar with Verilog design language, Verilog simulator and waveform debugging tools
- Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus
- Strong problem solving skills
- Team player with strong communication skills
EDUCATION:
Minimum B.Sc in Electrical or Computer Engineering (or equivalent)
Requisition Number: 181363
Job Function: Design
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
-
- The job has been sent to
What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
Senior DFT Engineer – Central DFX
The Role:
Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
The Person:
As a DFT Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
PRIMARY RESPONSIBILITY:
- Develop scan compression insertion and stitching flow automation
- Perform scan ATPG/DRC verification, pattern generation and simulation
- Collaborating with designers on STA, physical, power related issues
- Work with multi-functional teams and handling schedules
- The successful candidate may also be responsible of:
- Debugging and verifying block-/chip-level DFT/DFX features
- Porting or creating the DFT/DFX verification environment
- Block/chip test plan creation and development
- Stimulus writing and debug, and regression clean-up
KNOWLEDGE/SKILLS/ABILITY:
- DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus
- Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST
- Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
- Familiar with Verilog design language, Verilog simulator and waveform debugging tools
- Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus
- Strong problem solving skills
- Team player with strong communication skills
EDUCATION:
Minimum B.Sc in Electrical or Computer Engineering (or equivalent)
Requisition Number: 181363
Job Function: Design
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.