Job Details:
Job Description:
We're looking for a talented, self-motivated engineer to join our Design Verification (DV) team. We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification.
What We Build Our team develops and verifies high-speed SerDes IP, the physical layer technology that moves data at speeds from 10Gbps to 100Gbps+ across PCIe, Ethernet, and other industry-standard interfaces. Getting this right matters, the world's data moves through what we build.
What You'll Work On
Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP
Develop and maintain advanced SystemVerilog/UVM verification environments
Validate DSP datapaths against reference models
Contribute to FW/HW joint verification flows
Leverage AI-assisted tools as a core part of your daily engineering workflow
What We're Looking For
Solid hands-on SystemVerilog/UVM experience and ability to work independently
Strong Python scripting skills for verification automation
Deep understanding of digital design and computer architecture
Proven ability to take a verification task from plan to closure with minimal guidance
Experience collaborating across design, analog, and firmware teams
Analytical mindset, you dig until you find the root cause
What We Offer
A collaborative and innovative environment where great ideas come from every level of the team
A great place to work, we take the work seriously, and each other's success personally
Exposure to cutting-edge silicon and verification methodology
A real growth path with impact beyond your immediate role
Qualifications:
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
4–7 years of hands-on experience in hardware design verificationNice to Have
Experience verifying mixed-signal or analog IP
Familiarity with formal verification tools and methodologies
Knowledge of high-speed protocols such as PCIe or Ethernet
Background in DSP algorithm verification
Experience with AI-assisted engineering tools in a professional setting
Demonstrated track record of independent contribution to verification sign-off on complex IP