Posted 3y ago

USB IP Design Engineer (161763)

@ AMD
Taipei, Taiwan, Taiwan
OnsiteFull Time
Responsibilities:design RTL, mentor staff, develop IP
Requirements Summary:USB IP Design Engineer with RTL Verilog experience; knowledge of USB 3.x/Thunderbolt/PCIE; IO IP design expertise; MS/BS in EE or CS; fluent English.
Technical Tools Mentioned:Verilog, RTL design, HDL, PCIe, AMBA, USB 3.x, Thunderbolt
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Career Opportunities: USB IP Design Engineer (161763)

Requisition ID 161763 - Posted  - Taiwan - Taiwan - Taipei - Regular Salaried









































 


What you do at AMD changes everything 

 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

USB IP Design Engineer

 

THE ROLE:

Be part of AMD IO IP team, joining IP design work on host controller IP for next generation of leading-edge super high speed IO, up to 40 Gb/s. Establishes and maintains AMD high speed IO technological leadership position.

 

KEY RESPONSIBILITIES:

  • Takes part in host controller design, based on architectural requirement for next generation IO. Works on RTL code development for IP blocks in Verilog HDL and make sure functional correct and reusable for different product lines.
  • Deals with complex problems.
  • Makes technical decisions.
  • Coaches and mentors junior staff.

 

PREFERRED EXPERIENCE:

  • Specialized knowledge of USB 3.1/3.2/4.0 or Thunderbolt in protocol and link layers is a plus. Specialized knowledge of PCIE or AMBA is a plus.
  • Expert of Verilog RTL design on large size digital IP.
  • Fluent English on talking, presentation and writing documents.
  • Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
  • Can solve complex, novel and non-recurring problems.

 

ACADEMIC CREDENTIALS:

MS/BS degree of EE or CS

 

Location:

Taipei/Hsinchu, Taiwan

 

#LI-SC1



Requisition Number: 161763 
Job Function: Design  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.








 




































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Requisition ID 161763 - Posted  - Taiwan - Taiwan - Taipei - Regular Salaried


What you do at AMD changes everything 

 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

USB IP Design Engineer

 

THE ROLE:

Be part of AMD IO IP team, joining IP design work on host controller IP for next generation of leading-edge super high speed IO, up to 40 Gb/s. Establishes and maintains AMD high speed IO technological leadership position.

 

KEY RESPONSIBILITIES:

  • Takes part in host controller design, based on architectural requirement for next generation IO. Works on RTL code development for IP blocks in Verilog HDL and make sure functional correct and reusable for different product lines.
  • Deals with complex problems.
  • Makes technical decisions.
  • Coaches and mentors junior staff.

 

PREFERRED EXPERIENCE:

  • Specialized knowledge of USB 3.1/3.2/4.0 or Thunderbolt in protocol and link layers is a plus. Specialized knowledge of PCIE or AMBA is a plus.
  • Expert of Verilog RTL design on large size digital IP.
  • Fluent English on talking, presentation and writing documents.
  • Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
  • Can solve complex, novel and non-recurring problems.

 

ACADEMIC CREDENTIALS:

MS/BS degree of EE or CS

 

Location:

Taipei/Hsinchu, Taiwan

 

#LI-SC1



Requisition Number: 161763 
Job Function: Design  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Email this job to a friend
 
The job has been sent to
 
The job has been sent to


What you do at AMD changes everything 

 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

USB IP Design Engineer

 

THE ROLE:

Be part of AMD IO IP team, joining IP design work on host controller IP for next generation of leading-edge super high speed IO, up to 40 Gb/s. Establishes and maintains AMD high speed IO technological leadership position.

 

KEY RESPONSIBILITIES:

  • Takes part in host controller design, based on architectural requirement for next generation IO. Works on RTL code development for IP blocks in Verilog HDL and make sure functional correct and reusable for different product lines.
  • Deals with complex problems.
  • Makes technical decisions.
  • Coaches and mentors junior staff.

 

PREFERRED EXPERIENCE:

  • Specialized knowledge of USB 3.1/3.2/4.0 or Thunderbolt in protocol and link layers is a plus. Specialized knowledge of PCIE or AMBA is a plus.
  • Expert of Verilog RTL design on large size digital IP.
  • Fluent English on talking, presentation and writing documents.
  • Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
  • Can solve complex, novel and non-recurring problems.

 

ACADEMIC CREDENTIALS:

MS/BS degree of EE or CS

 

Location:

Taipei/Hsinchu, Taiwan

 

#LI-SC1



Requisition Number: 161763 
Job Function: Design  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.