ABOUT US

We're a small, fast-moving team developing RISC-V–based SoCs and the software

infrastructure to automate chip design. Our goal is to make advanced silicon development

faster, smarter, and more accessible.

We're looking for an entry-level Design Verification Engineer who is ready to take meaningful ownership of block-level and SoC-level verification. You'll work alongside our verification lead and RTL designers to build testbench infrastructure, write tests, and keep regression pipelines

healthy as the design evolves.

ROLE OVERVIEW

You'll implement and maintain verification components within our UVM/SystemVerilog

testbench environment, develop constrained-random and directed test scenarios, and

contribute to coverage closure. You'll get hands-on exposure to the full verification flow —

from environment bring-up to CI integration — with mentorship from senior engineers.

KEY RESPONSIBILITIES

- Develop and maintain block-level and SoC-level testbench components in

 SystemVerilog/UVM.

- Write directed, constrained-random, and coverage-driven tests for RISC-V CPU and

 SoC peripherals.

- Debug simulation failures and work with RTL designers to root-cause issues.

- Contribute to regression infrastructure and CI flows (Jenkins, GitLab CI, or similar).

- Implement functional coverage models and work toward coverage closure.

- Write and review SVA assertions to improve design observability.

- Support FPGA-based bring-up and firmware validation tasks.

- Document test plans, methodologies, and verification findings.

REQUIREMENTS

- BS, MS, or PhD in Electrical Engineer, Computer Engineering, or Computer Science

- Strong coursework digital design, VLSI, or computer architecture.

- Working knowledge of Verilog or SystemVerilog from courses or projects..

- Experience verifying at least one of: CPU cores, memory subsystems, or on-chip

 interconnects (AXI, AHB, TileLink, etc.).

- Familiarity with simulation tools (VCS, Xcelium, Questa, or Verilator).

- Basic scripting ability in Python, Tcl, or shell for test automation and debug.

- Solid debugging skills and attention to detail.

- Comfortable working in a startup environment with evolving priorities.

PREFERRED QUALIFICATIONS

- Exposure to RISC-V architecture or open-source cores (CVA6, Ibex, Rocket, etc.).

- Familiarity with formal verification concepts or tools (JasperGold, SymbiYosys).

- Experience with FPGA-based prototyping or co-simulation (Verilator + QEMU).

- Any contributions to open-source hardware or verification projects.

WHAT WE OFFER

- Hands-on exposure to full-SoC verification for a RISC-V chip from the ground up.

- Direct mentorship from experienced verification and RTL engineers.

- High visibility and real ownership in a small, expert team.

- Flexible work arrangements and PTO.

- Competitive compensation and benefits.