Alternate Job Titles
Senior Staff ASIC Physical Design Engineer
Sr Staff Physical Implementation Engineer
Senior Staff SoC Physical Design Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You take pride in solving the toughest physical design problems, the kind where advanced nodes, tight margins, and complex IP all collide. You’re the one who spots timing issues before they’re fire drills and who automates flows so the team can actually sleep before tape-out. If a tool throws a curveball, you debug and document, not just fix for yourself. You like working across teams—architecture, RTL, circuits—because you know every decision you make echoes downstream. You want your work to ship and matter. At Synopsys, you’ll own the path from RTL to GDS and raise the bar for everyone around you.
What You'll Be Doing
Own and optimize RTL-to-GDSII flow for UCIE IP, including STA and signoff (PrimeTime, IC Compiler II, ICV, RedHawk)
Integrate covercells, macros, and IP, ensuring clean abutment and QA
Automate tool flows, debug issues, and document best practices
Collaborate with architecture, RTL, and circuit teams on test chip development
Prepare tape-out views, documentation, and manage foundry checklists
The Impact You Will Have
Deliver high-quality, high-performance UCIE IP that meets aggressive PPA goals
Eliminate late-stage surprises through robust flows and early issue detection
Save team time by automating repeatable tasks and sharing solutions
Enable smooth integration for SoC teams and downstream users
Raise technical standards and reliability across projects
What You'll Need
9+ years in block-level physical design, including advanced nodes (7nm or below a plus)
Deep knowledge of floorplanning, P&R, timing closure, IR-drop/EM, LVS/DRC
Strong with PrimeTime, IC Compiler II/Fusion Compiler, ICV, RedHawk
Experience integrating complex IP and managing tape-outs
Scripting (Tcl, Python) and flow automation experience is a plus
Who You Are
You see tough timing paths as challenges, not problems
You explain complex tradeoffs clearly to any audience
You automate what you can and document what you learn
You support your team and know a successful tape-out is a group win
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Senior Staff ASIC Physical Design Engineer
Sr Staff Physical Implementation Engineer
Senior Staff SoC Physical Design Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You take pride in solving the toughest physical design problems, the kind where advanced nodes, tight margins, and complex IP all collide. You’re the one who spots timing issues before they’re fire drills and who automates flows so the team can actually sleep before tape-out. If a tool throws a curveball, you debug and document, not just fix for yourself. You like working across teams—architecture, RTL, circuits—because you know every decision you make echoes downstream. You want your work to ship and matter. At Synopsys, you’ll own the path from RTL to GDS and raise the bar for everyone around you.
What You'll Be Doing
Own and optimize RTL-to-GDSII flow for UCIE IP, including STA and signoff (PrimeTime, IC Compiler II, ICV, RedHawk)
Integrate covercells, macros, and IP, ensuring clean abutment and QA
Automate tool flows, debug issues, and document best practices
Collaborate with architecture, RTL, and circuit teams on test chip development
Prepare tape-out views, documentation, and manage foundry checklists
The Impact You Will Have
Deliver high-quality, high-performance UCIE IP that meets aggressive PPA goals
Eliminate late-stage surprises through robust flows and early issue detection
Save team time by automating repeatable tasks and sharing solutions
Enable smooth integration for SoC teams and downstream users
Raise technical standards and reliability across projects
What You'll Need
9+ years in block-level physical design, including advanced nodes (7nm or below a plus)
Deep knowledge of floorplanning, P&R, timing closure, IR-drop/EM, LVS/DRC
Strong with PrimeTime, IC Compiler II/Fusion Compiler, ICV, RedHawk
Experience integrating complex IP and managing tape-outs
Scripting (Tcl, Python) and flow automation experience is a plus
Who You Are
You see tough timing paths as challenges, not problems
You explain complex tradeoffs clearly to any audience
You automate what you can and document what you learn
You support your team and know a successful tape-out is a group win
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.