We Are:At Synopsys, we drive innovations that shape the world—from self-driving cars to AI and the cloud. As the global leader in chip design and verification, we empower the creation of high-performance silicon and software. Join us and transform the future through continuous technological advancement.
You Are:
You’re an accomplished ASIC Digital Design Verification expert with 10+ years of experience, skilled in UVM environments and passionate about building reliable, high-performance chips. You’re a hands-on leader and mentor, eager to leverage AI tools, formal verification, and the latest methodologies. Your collaborative spirit, analytical mindset, and “can do” attitude drive your success in fast-paced, innovative environments.
What You’ll Be Doing:
Partnering with design teams to define verification requirements
Developing test plans from specifications
Building and maintaining UVM testbenches and agents
Reviewing and improving test plans and code
Applying SVA and formal verification techniques
Implementing and analyzing coverage metrics
Leading and mentoring verification engineers
The Impact You Will Have:
Accelerate silicon development and time-to-market
Ensure robust, high-quality chip verification
Drive adoption of modern verification and AI tools
Reduce project risks through thorough coverage
Deliver complex IP for next-gen technologies
Mentor and grow technical teams
What You’ll Need:
B.Sc./M.Sc. in a relevant engineering field
10+ years in ASIC/UVM verification
SystemVerilog, C, Python, TCL/Perl proficiency
Experience with interface IPs (PCIe, CXL)
Familiarity with formal verification and AI tools
Who You Are:
Analytical and innovative
Collaborative communicator
Positive, adaptable leader and mentor
The Team You’ll Be A Part Of:
Join a high-impact HPC leadership team delivering complex IPs, leading engineers across multiple product verticals in a collaborative, innovative environment.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits. Details on salary and benefits will be provided during the hiring process.
You Are:
You’re an accomplished ASIC Digital Design Verification expert with 10+ years of experience, skilled in UVM environments and passionate about building reliable, high-performance chips. You’re a hands-on leader and mentor, eager to leverage AI tools, formal verification, and the latest methodologies. Your collaborative spirit, analytical mindset, and “can do” attitude drive your success in fast-paced, innovative environments.
What You’ll Be Doing:
Partnering with design teams to define verification requirements
Developing test plans from specifications
Building and maintaining UVM testbenches and agents
Reviewing and improving test plans and code
Applying SVA and formal verification techniques
Implementing and analyzing coverage metrics
Leading and mentoring verification engineers
The Impact You Will Have:
Accelerate silicon development and time-to-market
Ensure robust, high-quality chip verification
Drive adoption of modern verification and AI tools
Reduce project risks through thorough coverage
Deliver complex IP for next-gen technologies
Mentor and grow technical teams
What You’ll Need:
B.Sc./M.Sc. in a relevant engineering field
10+ years in ASIC/UVM verification
SystemVerilog, C, Python, TCL/Perl proficiency
Experience with interface IPs (PCIe, CXL)
Familiarity with formal verification and AI tools
Who You Are:
Analytical and innovative
Collaborative communicator
Positive, adaptable leader and mentor
The Team You’ll Be A Part Of:
Join a high-impact HPC leadership team delivering complex IPs, leading engineers across multiple product verticals in a collaborative, innovative environment.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits. Details on salary and benefits will be provided during the hiring process.