Sr Staff SoC Engineer(Backend)
Location: Beijing
Job Description:
Responsible for assisting our customers successfully tape out from Netlist to GDS by using Synopsys EDA tools.
Focus in the areas of design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS).
A secondary focus will be in static timing analysis, Low Power Static check and formal verification. Be working as a member of the customer's IC design team, leveraging their experience and Synopsys’ best practices to have immediate impact on their current project while transferring valuable knowledge for future projects.
Interacts regularly with customers to identify and eliminate barriers to project success.
Plans and manages delivery of own project-related tasks. Leverages entire Synopsys team to ensure project success. Provides feedback to R&D/AE on suggested tool enhancements or issues.
Works with or as Project Leader to develop technical proposals, working through project life cycle and produces consistently high-quality technical solutions.
Requirements:
- Typically requires BSEE or higher with 5+ years in physical design implementation role.
- Familiar with Floorplan, Place and route, DRC/LVS, IR drop, EM and Signal Integrity etc.
- Familiar with STA, Formal Verification and Synthesis is better.
- Demonstrate physical design implementation experience as an individual contributor or leading experience of bigger scale design.
- Demonstrate solid verbal and written English communication skills, and customer interfacing skills.
- Demonstrate the ability to work in a stressful environment with a broad array of individuals in a cross-functional team.
Location: Beijing
Job Description:
Responsible for assisting our customers successfully tape out from Netlist to GDS by using Synopsys EDA tools.
Focus in the areas of design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS).
A secondary focus will be in static timing analysis, Low Power Static check and formal verification. Be working as a member of the customer's IC design team, leveraging their experience and Synopsys’ best practices to have immediate impact on their current project while transferring valuable knowledge for future projects.
Interacts regularly with customers to identify and eliminate barriers to project success.
Plans and manages delivery of own project-related tasks. Leverages entire Synopsys team to ensure project success. Provides feedback to R&D/AE on suggested tool enhancements or issues.
Works with or as Project Leader to develop technical proposals, working through project life cycle and produces consistently high-quality technical solutions.
Requirements:
- Typically requires BSEE or higher with 5+ years in physical design implementation role.
- Familiar with Floorplan, Place and route, DRC/LVS, IR drop, EM and Signal Integrity etc.
- Familiar with STA, Formal Verification and Synthesis is better.
- Demonstrate physical design implementation experience as an individual contributor or leading experience of bigger scale design.
- Demonstrate solid verbal and written English communication skills, and customer interfacing skills.
- Demonstrate the ability to work in a stressful environment with a broad array of individuals in a cross-functional team.