Job Details:
Job Description:
- Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Supports SoC customers to ensure high-quality integration and verification of the IP block.
- Drives quality assurance compliance for smooth IP-SoC handoff.
Qualifications:
Good knowledge in IC validation methodologies and experience in conducting test & measurements for various IC timing/frequency/current/ voltage parameters
Good knowledge in FPGA architecture, Verilog/System Verilog is an added advantage
Experience in developing programming languages such as Python, tcl, C-programming, VBA, HTML etc. is an added advantage
Experience in handling various high speed test and measurement equipment such as ATE tester, high bandwidth real time/sampling oscilloscope, high frequency pulse/signal , power supply is an added advantage