Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.
Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.
A sustained driver of Keysight’s success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team.
The role is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life—immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.
Responsibilities
- Set and drive the technical strategy for digital IP, block-level design, verification, and full-chip integration—aligning architectural choices to product differentiation, schedule, and long-term reuse.
- Lead, mentor, and scale a high-performing organization of architects, RTL designers, and verification engineers; establish clear technical expectations and a culture of ownership and excellence.
- Own program delivery from concept through tapeout and into productization—planning resources, managing schedules and milestones, and proactively driving risk retirement and trade-off decisions.
- Influence outcomes across the broader silicon ecosystem by partnering tightly with physical design, DFT/test, IP, software/firmware, packaging, systems engineering, and foundry/OSAT partners.
- Establish and enforce robust quality and signoff discipline, including design reviews, coding standards, verification closure, timing and power closure, area/constraints management, and manufacturability/yield considerations.
- Build a world-class team: recruit and hire top talent, develop technical leaders, and manage performance and career growth to retain key capabilities.
- Manage the operating model for the team, including budget ownership, EDA/tool strategy, license planning, and vendor/partner selection.
- Drive continuous improvement in productivity and predictability through design flows, automation, CI/regression infrastructure, and disciplined IP reuse strategies.
Qualifications
Must-have Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 7+ years of digital IC/ASIC development experience, with demonstrated progression in technical leadership (people management experience preferred).
- Strong hands-on depth in RTL micro-architecture and implementation (SystemVerilog/Verilog/VHDL), synthesis, STA/timing closure, and power/performance optimization.
Preferred Qualifications
- Deep expertise in modern verification, including constrained-random methodology, formal techniques, and acceleration/emulation.
- Working knowledge of the full silicon lifecycle and cross-functional handoffs, including physical design, DFT/scan, signoff flows, and foundry enablement.
- Proven ability to deliver complex programs to tapeout—building credible plans, managing dependencies and risk, and driving alignment across multiple teams.
- Proficiency with industry-standard EDA environments (e.g., Cadence and Siemens/Mentor) and productivity scripting/automation (Python, Tcl, and/or Ruby).
- Executive-level communication skills and strong stakeholder management—able to translate technical trade-offs into clear decisions and commitments.
- Sound judgment under schedule pressure, with a track record of prioritizing the right trade-offs while maintaining quality.
- Demonstrated people leadership strengths, including mentoring and coaching engineers, developing technical leaders, and building a strong team culture of accountability, learning, and engineering excellence.
Most offers will be between the minimum and the midpoint of the Salary Range listed below.
MIN $151,000.00 - MAX $253,000.00
#LI-MO1
Note: For other locations, pay ranges will vary by region
US Employees may be eligible for the following benefits:
- Medical, dental and vision
- Health Savings Account
- Health Care and Dependent Care Flexible Spending Accounts
- Life, Accident, Disability insurance
- Business Travel Accident and Business Travel Health
- 401(k) Plan
- Flexible Time Off, Paid Holidays
- Paid Family Leave
- Discounts, Perks
- Tuition Reimbursement
- Adoption Assistance
- ESPP (Employee Stock Purchase Plan)
Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***