Posted 1mo ago

ASIC Engineer

@ Falcomm
Atlanta, Georgia, United States
OnsiteFull Time
Responsibilities:designing blocks, developing RTL, collaborating teams
Requirements Summary:Bachelor’s or Master’s in Electrical/Computer Engineering or related field; 1-3 years ASIC design experience; RTL (Verilog/SystemVerilog); digital and analog/mixed-signal design knowledge; ASIC tool flows (Synopsys/Cadence); UVM preferred; onsite in Atlanta.
Technical Tools Mentioned:Verilog, SystemVerilog, EDA tools, Synopsys, Cadence, UVM, HDL simulators, Python, TCL
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Job Description

Are you passionate about building advanced semiconductor systems that power next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world products through energy-efficient RF power amplifier and wireless solutions. Our mission is to push the boundaries of performance, efficiency, and integration in modern communication systems.

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital integrated circuits that interface with our RF technologies. This role will contribute to the design, implementation, and verification of ASIC components within larger system-on-chip platforms. The position requires strong collaboration with RFIC, analog, verification, and system engineering teams to deliver high-performance silicon solutions.

Responsibilities:

  • Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout
  • Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area
  • Collaborate with RFIC, analog, and system engineers to integrate digital logic within RF and mixed-signal chip architectures.
  • Perform synthesis, timing closure, and power optimization
  • Work with verification engineers to define testbenches and ensure robust design validation
  • Support functional verification and debugging of ASIC components in collaboration with verification teams.
  • Assist with synthesis, timing analysis, and physical implementation activities to ensure design readiness for tape-out.
  • Contribute to silicon bring-up, debugging, and post-silicon validation activities.
  • Document design architecture, implementation details, and verification results.