Career Opportunities: SMTS Silicon Design Engineer (178201)
What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE ROLE:
PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD’s projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification.
THE PERSON:
People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role.
KEY RESPONSIBILITIES:
- Develop and update infrastructure and environment for IP level design verification.
- Closely working with Design and Architecture team to develop new verification component
- Responsible for PCIe SS IP new features verification plan and verification closure
- Solid background with ASIC design verification flow and multiple ASIC tape out experience with 6~10+ years
- Team leading experience and experienced on testbench architecture.
- Solid knowledge on UVM, SystemVerilog , Verilog is a must
- SoC system or sub-system work experience is a plus
- Fluent written English for technical discussion among global team, vocal is a plus
- Knowledge on High speed IO/PCIE or Serdes PHY is a big plus
- Knowledge on C++ or script language like perl, python, ruby is a plus
ACADEMIC CREDENTIALS:
- Solid education background, 211 master is must, 985 preferred. Or Top 100 ranking oversea
- Candidate is preferred to be MSEE with 6~10+ years, or BSEE with minimum of 8-years’ experience in digital ASIC/SOC design verification.
LOCATION:
Shanghai
#LI-JG2
Requisition Number: 178201
Country/Region/Location: China State/Province: Shanghai City: Shanghai
Job Function: Design
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What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE ROLE:
PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD’s projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification.
THE PERSON:
People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role.
KEY RESPONSIBILITIES:
- Develop and update infrastructure and environment for IP level design verification.
- Closely working with Design and Architecture team to develop new verification component
- Responsible for PCIe SS IP new features verification plan and verification closure
- Solid background with ASIC design verification flow and multiple ASIC tape out experience with 6~10+ years
- Team leading experience and experienced on testbench architecture.
- Solid knowledge on UVM, SystemVerilog , Verilog is a must
- SoC system or sub-system work experience is a plus
- Fluent written English for technical discussion among global team, vocal is a plus
- Knowledge on High speed IO/PCIE or Serdes PHY is a big plus
- Knowledge on C++ or script language like perl, python, ruby is a plus
ACADEMIC CREDENTIALS:
- Solid education background, 211 master is must, 985 preferred. Or Top 100 ranking oversea
- Candidate is preferred to be MSEE with 6~10+ years, or BSEE with minimum of 8-years’ experience in digital ASIC/SOC design verification.
LOCATION:
Shanghai
#LI-JG2
Requisition Number: 178201
Country/Region/Location: China State/Province: Shanghai City: Shanghai
Job Function: Design
-
- The job has been sent to
What you do at AMD changes everything
We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
THE ROLE:
PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD’s projects. Shanghai PCIe team contributed a lot on the first PCIe Gen4 product and are working on Gen5 product. So, this role provides a great opportunity for working on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification.
THE PERSON:
People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role.
KEY RESPONSIBILITIES:
- Develop and update infrastructure and environment for IP level design verification.
- Closely working with Design and Architecture team to develop new verification component
- Responsible for PCIe SS IP new features verification plan and verification closure
- Solid background with ASIC design verification flow and multiple ASIC tape out experience with 6~10+ years
- Team leading experience and experienced on testbench architecture.
- Solid knowledge on UVM, SystemVerilog , Verilog is a must
- SoC system or sub-system work experience is a plus
- Fluent written English for technical discussion among global team, vocal is a plus
- Knowledge on High speed IO/PCIE or Serdes PHY is a big plus
- Knowledge on C++ or script language like perl, python, ruby is a plus
ACADEMIC CREDENTIALS:
- Solid education background, 211 master is must, 985 preferred. Or Top 100 ranking oversea
- Candidate is preferred to be MSEE with 6~10+ years, or BSEE with minimum of 8-years’ experience in digital ASIC/SOC design verification.
LOCATION:
Shanghai
#LI-JG2
Requisition Number: 178201
Country/Region/Location: China State/Province: Shanghai City: Shanghai
Job Function: Design