Posted 3y ago

MTS Silicon Design Engineer (178163)

@ AMD
Shanghai, Shanghai, China
OnsiteFull Time
Responsibilities:IP development, Testbench creation, Verification execution
Requirements Summary:MTS Silicon Design Engineer with strong verification skills; IP development and testbench experience; MS with 2+ years or BS with 3+ years in EE/CS.
Technical Tools Mentioned:UVM, SystemVerilog, PCIE, Linux
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Job Description

Career Opportunities: MTS Silicon Design Engineer (178163)

Requisition ID 178163 - Posted  - China - Shanghai - Shanghai - Regular Salaried









































 

What you do at AMD changes everything

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

 

THE ROLE:

For all stages of verification on IP, including developing testbench, model,

assertions/checkers/monitors, test plan & test development, regressions, and infrastructure

development.

 

THE PERSON:

  • Strong self-driving ability
  • Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • IP new feature development and verification
  • Building testbench, creating test plan and debugging regression
  • Apply necessary verification methodologies to ASIC design, such as UVM, coverage, assertion, randomization, etc. to achieve the verification goals
  • Create script to enhance verification efficiency.

 

PREFERRED EXPERIENCE:

  • Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan etc.)
  • Familiar with PCIE.
  • Familiar with SV/UVM.
  • Familiar with Linux Environment.

 

ACADEMIC CREDENTIALS:

Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 3+ years working experiences

LOCATION:

Shanghai

#LI-JG2



Requisition Number: 178163 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  








 




































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Requisition ID 178163 - Posted  - China - Shanghai - Shanghai - Regular Salaried

What you do at AMD changes everything

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

 

THE ROLE:

For all stages of verification on IP, including developing testbench, model,

assertions/checkers/monitors, test plan & test development, regressions, and infrastructure

development.

 

THE PERSON:

  • Strong self-driving ability
  • Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • IP new feature development and verification
  • Building testbench, creating test plan and debugging regression
  • Apply necessary verification methodologies to ASIC design, such as UVM, coverage, assertion, randomization, etc. to achieve the verification goals
  • Create script to enhance verification efficiency.

 

PREFERRED EXPERIENCE:

  • Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan etc.)
  • Familiar with PCIE.
  • Familiar with SV/UVM.
  • Familiar with Linux Environment.

 

ACADEMIC CREDENTIALS:

Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 3+ years working experiences

LOCATION:

Shanghai

#LI-JG2



Requisition Number: 178163 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

Email this job to a friend
 
The job has been sent to
 
The job has been sent to

What you do at AMD changes everything

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

 

THE ROLE:

For all stages of verification on IP, including developing testbench, model,

assertions/checkers/monitors, test plan & test development, regressions, and infrastructure

development.

 

THE PERSON:

  • Strong self-driving ability
  • Should have excellent communication skills (both written and oral)
  • Strong problem-solving skills

 

KEY RESPONSIBILITIES:

  • IP new feature development and verification
  • Building testbench, creating test plan and debugging regression
  • Apply necessary verification methodologies to ASIC design, such as UVM, coverage, assertion, randomization, etc. to achieve the verification goals
  • Create script to enhance verification efficiency.

 

PREFERRED EXPERIENCE:

  • Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan etc.)
  • Familiar with PCIE.
  • Familiar with SV/UVM.
  • Familiar with Linux Environment.

 

ACADEMIC CREDENTIALS:

Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 3+ years working experiences

LOCATION:

Shanghai

#LI-JG2



Requisition Number: 178163 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design