As a member of our Physical Design group, you will take an integral part in bringing large scale SoCs to life, helping us deliver the next generation of Apple's ground-breaking products.
You will own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification.
Are you ready to join some of the world's leading engineers and work with state of the art design flows and process technology?
If you possess the knowledge and experience in any of the physical design domains and practices with track record of tape-outs in sub-micron technology, come join our group!

Description

As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
* Implementation - Block level PnR, floor-planning, clock, power planning and distribution.
* Verification and Analysis - Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )

Minimum Qualifications

• 3+ years of experience in physical design of large-scale SoCs
• B.Sc / M.Sc Electric Engineering / Computer Engineering
• Extensive experience with one of the place & route tools (Synopsys / Cadence)
• Scripting and Programming experience using either TCL or Python or Perl, or known Shell scripting languages

Preferred Qualifications

• Knowledge in Verilog – advantage