Job Details:
Job Description:
- Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing
- Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
- Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
- Analyzes results and makes recommendations to fix violations for current and future product architecture.
- Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
- Possesses hands on expertise in various process nodes full chip physical integration, system level place and route and system level verification signoff.
Qualifications:
Education Requirements:
Bachelor's degree in computer engineering, electronic Engineering or related field.
Minimum Qualifications
5+ years of relevant experience in the following areas:
- Have multiple tape-out experience in deep submicron process nodes
- in depth, extensive knowledge and hands-on experience in physical design flow and relevant EDA tools
- in depth, extensive knowledge and hands-on experience in physical design signoff flow, such as STA flow, LEC flow, ERC flow and DRC flow.
- Hands-on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages of VHDL and Verilog.
- Experience of mentoring junior team members and charting their development for success.
- Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Preferred Requirements:
- Bachelor or master's degree in computer engineering, Electronic Engineering or related field.
- 5+ years of experience in the following areas:
- Physical design involving multiple clock domains and clock, power management.
- Low power design, tools and methodologies. Power intent UPF specifications.